[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/produc

[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700

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[RISCV] Add software pipeliner support (#117546)

This patch adds basic support of `MachinePipeliner` and disable
it by default.

The functionality should be OK and all llvm-test-suite tests have

[RISCV] Add software pipeliner support (#117546)

This patch adds basic support of `MachinePipeliner` and disable
it by default.

The functionality should be OK and all llvm-test-suite tests have
passed.

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[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968

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[RISCV] Add tune info for postra scheduling direction (#115864)

The results differ on different platforms so it is really hard to
determine a common default value.

Tune info for postra scheduli

[RISCV] Add tune info for postra scheduling direction (#115864)

The results differ on different platforms so it is really hard to
determine a common default value.

Tune info for postra scheduling direction is added and CPUs can
set their own preferable postra scheduling direction.

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[RISCV] Add TuneDisableLatencySchedHeuristic

This tune feature will disable latency scheduling heuristic.

This can reduce the number of spills/reloads but will cause some
regressions on some cores.

[RISCV] Add TuneDisableLatencySchedHeuristic

This tune feature will disable latency scheduling heuristic.

This can reduce the number of spills/reloads but will cause some
regressions on some cores.

CPU may add this tune feature if they find it's profitable.

Reviewers: lukel97, michaelmaitland, asb, preames, mshockwave, topperc

Reviewed By: michaelmaitland, mshockwave, topperc

Pull Request: https://github.com/llvm/llvm-project/pull/115858

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[RISCV] Remove getPostRAMutations (#117527)

We are using `PostMachineScheduler` instead of `PostRAScheduler`
since #68696.

The hook `getPostRAMutations` is only used in `PostRAScheduler` so
it is a

[RISCV] Remove getPostRAMutations (#117527)

We are using `PostMachineScheduler` instead of `PostRAScheduler`
since #68696.

The hook `getPostRAMutations` is only used in `PostRAScheduler` so
it is actually dead code for RISC-V now.

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[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional schedu

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)


This is based on other targets like PPC/AArch64 and some experiments.

This PR will only enable bidirectional scheduling and tracking register
pressure.

Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.

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[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

Fixed length vectors use scalable vector containers. With Zve32* and not
Zvl64b, vscale is a 0.5 due RVVBitsPerBlock being

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

Fixed length vectors use scalable vector containers. With Zve32* and not
Zvl64b, vscale is a 0.5 due RVVBitsPerBlock being 64.

To support this correctly we need to lower RVVBitsPerBlock to 32 and
change our type mapping. But we need to RVVBitsPerBlock to alway be
>= ELEN. This means we need two different mapping depending on ELEN.

That is a non-trivial amount of work so disable fixed lenght vectors
without Zvl64b for now.

We had almost no tests for Zve32x without Zvl64b which is probably why
we never realized that it was broken.

Fixes #102352.

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[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375)

Instead of std::unique_ptr<RegisterBankInfo>. This allows us to return a
RISCVRegisterBankInfo* from getRegBan

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375)

Instead of std::unique_ptr<RegisterBankInfo>. This allows us to return a
RISCVRegisterBankInfo* from getRegBankInfo so we can avoid a
static_cast.

This does require an additional header file to be included in
RISCVSubtarget.h, but I don't think it's a big deal.

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[RISCV][GISEL] Do not initialize GlobalISel objects unless needed (#98233)

Prior to this commit, we created the GlobalISel objects in the
RISCVSubtarget constructor, even if we are not running Glob

[RISCV][GISEL] Do not initialize GlobalISel objects unless needed (#98233)

Prior to this commit, we created the GlobalISel objects in the
RISCVSubtarget constructor, even if we are not running GlobalISel. This
patch moves creation of the GlobalISel objects into their getters, which
ensures that we only create these objects if they are actually needed.
This helps since some of the constructors of the GlobalISel objects have
a significant amount of code.

We make the `unique_ptr`s `mutable` since GlobalISel passes only have
access to `const TargetSubtargetInfo` through `MF.getSubtarget()`.

This patch is tested by the fact that all existing RISC-V GlobalISel
tests remain passing.

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[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-l

[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget->enableSubRegLiveness()`
has been changed to `MRI->subRegLivenessEnabled()` to make sure the
option properly applies.

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[RISCV] Use TableGen-based macro fusion (#72224)

We convert existed macro fusions to TableGen.

Bacause `Fusion` depend on `Instruction` definitions which is defined
below `RISCVFeatures.td`, so

[RISCV] Use TableGen-based macro fusion (#72224)

We convert existed macro fusions to TableGen.

Bacause `Fusion` depend on `Instruction` definitions which is defined
below `RISCVFeatures.td`, so we recommend user to add fusion features
when defining new processor.

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[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)

This is like what AArch64 has done in #71166 except that we don't
handle `HasMinSize` case now.

[RISCV] Add searchable table for tune information (#66193)

There are many information that can be used for tuning, like
alignments, cache line size, etc. But we can't make all of them
`SubtargetFe

[RISCV] Add searchable table for tune information (#66193)

There are many information that can be used for tuning, like
alignments, cache line size, etc. But we can't make all of them
`SubtargetFeature` because some of them are not with enumerable
value, for example, `PrefetchDistance` used by `LoopDataPrefetch`.

In this patch, a searchable table `RISCVTuneInfoTable` is added,
in which each entry contains the CPU name and all tune information
defined in `RISCVTuneInfo`. Each field of `RISCVTuneInfo` should
have a default value and processor definitions can override the
default value via `let` statements.

We don't need to define a `RISCVTuneInfo` for each processor and
it will use the default value (which is for `generic`) if no
`RISCVTuneInfo` defined.

For processors in the same series, a subclass can inherit from
`RISCVTuneInfo` and override the fields. And we can also override
the fields in processor definitions if there are some differences
in the same processor series.

When initilizing `RISCVSubtarget`, we will use `TuneCPU` as the
key to serach the tune info table. So, the behavior here is if
we don't specify the tune CPU, we will use specified `CPU`, which
is expected I think.

This patch almost undoes 61ab106, in which I added tune features
of preferred function/loop alignments. More tune information can
be added in the future.

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[RISCV] Remove XLen field from RISCVSubtarget [nfc]

The isRV64 field contains the same information, and we can derive XLen
from that.

Differential Revision: https://reviews.llvm.org/D159306

[RISCV] Kill off redundant field XLenVT [nfc]

We're already tracking XLen, we can compute XLenVt from that. Note that XLen itself should probably be driven from IsRV64 (the processor flag), but I'm

[RISCV] Kill off redundant field XLenVT [nfc]

We're already tracking XLen, we can compute XLenVt from that. Note that XLen itself should probably be driven from IsRV64 (the processor flag), but I'm leaving that to a separate change (with review).

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[RISCV] Enable alias analysis by default

In llvm alias analysis is off by default now.
This patch enable alias analysis on RISCV target during code generation by default,
and this makes more chances

[RISCV] Enable alias analysis by default

In llvm alias analysis is off by default now.
This patch enable alias analysis on RISCV target during code generation by default,
and this makes more chances for improving performance.
Modified related test cases.

Differential Revision: https://reviews.llvm.org/D157250

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[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the ta

[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the target. Individual RegisterBanks cannot be constructed with HwMode information as construction is generated by TableGen, but a RegisterBankInfo subclass can provide the HwMode as a constructor argument. The HwMode is used to select the appropriate RegisterBank size from an array relating sizes to RegisterBanks.

Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed).

Reviewed By: simoncook, craig.topper

Differential Revision: https://reviews.llvm.org/D76007

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[CodeGen][RISCV] Change Shadow Call Stack Register to X3

ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/

[CodeGen][RISCV] Change Shadow Call Stack Register to X3

ShadowCallStack implementation uses s2 register on RISC-V, but that
choice is problematic for reasons described in:

https://lists.riscv.org/g/sig-toolchains/message/544,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and
https://github.com/google/android-riscv64/issues/72

The concern over the register choice was also brought up in
https://reviews.llvm.org/D84414.

https://reviews.llvm.org/D84414#2228666 said:

```
"If the register choice is the only concern about this work, then I think
we can probably land it as-is and fixup the register choice if we see
major drawbacks later. Yes, it's an ABI issue, but on the other hand the
shadow call stack is not a standard ABI anyway.""
```

Since we have now found a sufficient reason to fixup the register
choice, we should go ahead and update the implementation. We propose
using x3(gp) which is now the platform register in the RISC-V ABI.

Reviewed By: asb, hiraditya, mcgrathr, craig.topper

Differential Revision: https://reviews.llvm.org/D146463

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV] Enable subregister liveness by default

This commit enable the subregister liveness by default in RISC-V.

It was previously disabled in https://reviews.llvm.org/D129646 after a previous atte

[RISCV] Enable subregister liveness by default

This commit enable the subregister liveness by default in RISC-V.

It was previously disabled in https://reviews.llvm.org/D129646 after a previous attempt to enabled it https://reviews.llvm.org/D128016.

We believe that https://reviews.llvm.org/D129735 fixes the issue that caused it to be disabled.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D145546

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Use llvm::has_single_bit<uint32_t> (NFC)

This patch replaces isPowerOf2_32 with llvm::has_single_bit<uint32_t>
where the argument is wider than uint32_t.

[RISCV] Default to -ffixed-x18 for Fuchsia

Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.

Reviewed By: phose

[RISCV] Default to -ffixed-x18 for Fuchsia

Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D143355

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[RISCV] clang-format #include. NFC

[RISCV] Use llvm::bit_floor and std::clamp (NFC)