[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

The DwarfDebug.cpp implementation expects the epilogue instructions to
have source location of last non-debug instruction

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

The DwarfDebug.cpp implementation expects the epilogue instructions to
have source location of last non-debug instruction after which the epilogue
instructions are inserted. The epilogue_begin is set on location of the first
FrameDestroy instruction with source line information that has been seen in
the epilogue basic block.

In the trunk, the risc-v backend sets the epilogue_begin after the epilogue has
actually begun i.e. after callee saved register reloads and the source line
information is not set on those reload instructions. This is leading to #120553
where, while debugging, breaking on or single stepping to the epilogue_begin
location will make accessing the variables from wrong place as the FP has been
restored to the parent frame's FP.

To fix that, this patch sets FrameSetup/FrameDestroy flags on the callee saved
register spill/reload instructions which is actually correct. Then the
RISCVInstrInfo::loadRegFromStackSlot uses FrameDestroy flag to identify a
reload of the callee saved register in the epilogue and copies the source
line information from insert position instruction to that reload instruction.

Requires PR #120622

Fixes #120553

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[RISCV] Stack clash protection for dynamic alloca (#122508)

Create a probe loop for dynamic allocation and add the corresponding
SelectionDAG support in order to use it.

[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)

This seems like an oversight when copying code from other backends.

[RISCV] Add stack clash vector support (#119458)

Use the probe loop structure to allocate vector code in the stack as
well. We add the pseudo instruction RISCV::PROBED_STACKALLOC_RVV to
differenti

[RISCV] Add stack clash vector support (#119458)

Use the probe loop structure to allocate vector code in the stack as
well. We add the pseudo instruction RISCV::PROBED_STACKALLOC_RVV to
differentiate from the normal loop.

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[llvm][RISCV] Set ScalableVector stack id in proper place (#117862)

Without this patch ScalableVector frame index property is used before
assignment. More precisely, let's take a look at
RISCVFram

[llvm][RISCV] Set ScalableVector stack id in proper place (#117862)

Without this patch ScalableVector frame index property is used before
assignment. More precisely, let's take a look at
RISCVFrameLowering::assignCalleeSavedSpillSlots. In this function we
divide callee saved registers on scalar and vector ones, based on
ScalableVector property of their frame indexes:
```
...
const auto &UnmanagedCSI = getUnmanagedCSI(*MF, CSI);
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI);
...
```
But we assign ScalableVector property several lines below:
```
...
auto storeRegToStackSlot = [&](decltype(UnmanagedCSI) CSInfo) {
for (auto &CS : CSInfo) {
// Insert the spill to the stack frame.
Register Reg = CS.getReg();
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg),
CS.getFrameIdx(), RC, TRI, Register());
}
};
storeRegToStackSlot(UnmanagedCSI);
...
```
Due to it, list of RVV callee saved registers will always be empty.
Currently this problem doesn't appear, but if you slightly change the
code and, for example, put some instructions between scalar and vector
spills, the resulting code will be ill formed.

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[RISCV] Rename a lambda to have plural nouns to reflect that it contains a loop. NFC

storeRegToStackSlot contains a loop that stores multiple registers
to multiple slots.

[RISCV] Compute liveins for new basic blocks in emitStackProbeInline.

Fixes expensive check failures from #117612.

[RISCV] Add stack clash protection (#117612)

Enable `-fstack-clash-protection` for RISCV and stack probe for function
prologues.
We probe the stack by creating a loop that allocates and probe the

[RISCV] Add stack clash protection (#117612)

Enable `-fstack-clash-protection` for RISCV and stack probe for function
prologues.
We probe the stack by creating a loop that allocates and probe the stack
in ProbeSize chunks.
We emit an unrolled probe loop for small allocations and emit a variable
length probe loop for bigger ones.

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[NFC][RISCV] Remove CFIIndex argument from allocateStack (#117871)

Calculates CFIIndex inside RISCVFrameLowering::allocateStack instead of
sending it by argument.

[RISCV] Use RISCVSubtarget::is64Bit() instead of hasFeature(RISCV::Feature64Bit). NFC

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)

We can move the logic from adjustStackForRVV into adjustReg, which
results in the remaining logic being trivially inlin

[RISCV] Consolidate VLS codepaths in stack frame manipulation [nfc] (#117605)

We can move the logic from adjustStackForRVV into adjustReg, which
results in the remaining logic being trivially inlined to the two
callers and allows a duplicate copy of the same logic in
eliminateFrameIndex to be pruned.

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[RISCV] Fix double counting scalar CSRs with Zcmp when emitting cfi_offset for RVV CSRs. (#117408)

getCalleeSavedStackSize() already contains RVPushStackSize. Don't
subtract it again.

[NFC][RISCV] Refactor allocation of the stack space (#116625)

Separates the stack allocations from prologue in preparation for the
stack clash protection support.

[RISCV] Fix double counting CSRs with Zcmp in RISCVFrameLowering::getFrameIndexReference. (#117207)

The Zcmp callee saved registers are already accounted for in
getCalleeSavedStackSize(). Subtracti

[RISCV] Fix double counting CSRs with Zcmp in RISCVFrameLowering::getFrameIndexReference. (#117207)

The Zcmp callee saved registers are already accounted for in
getCalleeSavedStackSize(). Subtracting RVPushStackSize subtracts
them a second time leading to incorrect stack offsets during frame
index elimination.

This should have been removed in
0de2b26942f890a6ec84cd75ac7abe3f6f2b2e37
when Zcmp handling was changed. Prior to that, RVPushStackSize was
not included in getCalleeSavedStackSize(). The commit message at the
time noted that Zcmp+RVV was likely broken.

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[RISCV][NFC] refactor CFI emitting (#114227)

This patch refactor PR https://github.com/llvm/llvm-project/pull/110810
to remove code duplication.

[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)

This patch follows https://github.com/llvm/llvm-project/pull/112477.
Previously `-fsanitize=shadow-call-stack` (which get transform to
`Attr

[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)

This patch follows https://github.com/llvm/llvm-project/pull/112477.
Previously `-fsanitize=shadow-call-stack` (which get transform to
`Attribute::ShadowCallStack`) is used for enable both hardware and
software shadow stack, and another option `-force-sw-shadow-stack` is
needed if the user wants to use the software shadow stack where hardware
software shadow stack could be supported. It decouples both by using the
string attribute `hw-shadow-stack` to distinguish from the software
shadow stack attribute.

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[RISCV] fix SP recovery in varargs functions (#114316)

This patch fixes sp recovery in the epilogue in varargs functions when
fp register is presented and second sp adjustment is applied.

Source

[RISCV] fix SP recovery in varargs functions (#114316)

This patch fixes sp recovery in the epilogue in varargs functions when
fp register is presented and second sp adjustment is applied.

Source of the issue: https://github.com/llvm/llvm-project/pull/110809

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[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s

[RISCV][CFI] add function epilogue cfi information (#110810)

This patch adds CFI instructions in the function epilogue.

Before patch:
addi sp, s0, -32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
addi sp, sp, 32
ret

After patch:
addi sp, s0, -32
.cfi_def_cfa sp, 32
ld ra, 24(sp) # 8-byte Folded Reload
ld s0, 16(sp) # 8-byte Folded Reload
ld s1, 8(sp) # 8-byte Folded Reload
.cfi_restore ra
.cfi_restore s0
.cfi_restore s1
addi sp, sp, 32
.cfi_def_cfa_offset 0
ret

This functionality is already present in `riscv-gcc`, but it’s not in
`clang` and this slightly impairs the `lldb` debugging experience, e.g.
backtrace.

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[RISCV] Refactor FP, SP and RA in RISCVFrameLowering.cpp. NFC (#113818)

Those registers are too fragmented in terms of usage, some are hard
coded and some are retrieved by calling function. Also so

[RISCV] Refactor FP, SP and RA in RISCVFrameLowering.cpp. NFC (#113818)

Those registers are too fragmented in terms of usage, some are hard
coded and some are retrieved by calling function. Also some have
comments for alias name, some don't.

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[RISC-V] Fix check of minimum vlen. (#114055)

If we have a minimum vlen, we were adjusting StackSize to change the
unit from vscale to bytes, and then calculating the required padding
size for ali

[RISC-V] Fix check of minimum vlen. (#114055)

If we have a minimum vlen, we were adjusting StackSize to change the
unit from vscale to bytes, and then calculating the required padding
size for alignment in bytes. However, we then used that padding size as
an offset in vscale units, resulting in misplaced stack objects.

While it would be possible to adjust the object offsets by dividing
AlignmentPadding by ST.getRealMinVLen() / RISCV::RVVBitsPerBlock, we can
simplify the calculation a bit if instead we adjust the alignment to be
in vscale units.

@topperc This fixes a bug I am seeing after #110312, but I am not 100%
certain I am understanding the code correctly, could you please see if
this makes sense to you?

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[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that

[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.

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[RISCV] fix SP recovery in a function epilogue (#110809)

Currently, in the cases when fp register is presented and sp register is
adjusted at the second time, sp recovery in a function epilogue isn

[RISCV] fix SP recovery in a function epilogue (#110809)

Currently, in the cases when fp register is presented and sp register is
adjusted at the second time, sp recovery in a function epilogue isn't
performed in the best way, for example:
```
lui a0, 2
sub sp, s0, a0
addi a0, a0, -2044
add sp, sp, a0
```

This patch improves sp register recovery in such cases and the code
snippet above becomes:
```
addi sp, s0, -2044
```

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[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

If we know vlen is a multiple of 16, we don't need any alignment
padding.

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

If we know vlen is a multiple of 16, we don't need any alignment
padding.

I wrote the code so that it would generate the minimum amount of padding
if the stack align was 32 or larger or if RVVBitsPerBlock was smaller
than half the stack alignment.

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[RISCV] Use RVVBitsPerBlock in assignRVVStackObjectOffsets and adjustReg. NFC (#109848)

I think the 8 here represents RVVBitsPerBlock / 8.

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)

The grouped vector register is modeled as a single register, e.g. V2M2,
which is actually V2 and V3. We need to decomp

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)

The grouped vector register is modeled as a single register, e.g. V2M2,
which is actually V2 and V3. We need to decompose the grouped vector
register(if any) to individual vector register when emitting CFIs in
prologue.

Fixed https://github.com/llvm/llvm-project/issues/94500

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