[RISCV] Remove Zbproposedc extension

This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't

[RISCV] Remove Zbproposedc extension

This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't think it makes sense to keep them in bitmanip. It
will eventually cause a conflict if/when Zce is implemented in llvm.

Differential Revision: https://reviews.llvm.org/D110871

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[RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension

Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension for consistency

Reviewed By: HsiangKai, asb

Diff

[RISCV] Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension

Rename prefix `FeatureExt*` to `FeatureStdExt*` for all sub-extension for consistency

Reviewed By: HsiangKai, asb

Differential Revision: https://reviews.llvm.org/D108187

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[RISCV] Update the version number to v0.10 for vector.

v0.10 is tagged in V specification. Update the version to v0.10.

Differential Revision: https://reviews.llvm.org/D95680

[RISCV] Update V extension to v1.0-draft 08a0b464.

Differential Revision: https://reviews.llvm.org/D94583

[RISCV] Add attribute support for all supported extensions

This adds support for ".attribute arch" for all extensions that are
currently supported by the compiler.

Differential Revision: https://re

[RISCV] Add attribute support for all supported extensions

This adds support for ".attribute arch" for all extensions that are
currently supported by the compiler.

Differential Revision: https://reviews.llvm.org/D94931

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[RISCV] Don't include CodeGen layer files in MC layer

-Use MCRegister instead of Register in MC layer.
-Move some enums from RISCVInstrInfo.h to RISCVBaseInfo.h to be with other TSFlags bits.

Diffe

[RISCV] Don't include CodeGen layer files in MC layer

-Use MCRegister instead of Register in MC layer.
-Move some enums from RISCVInstrInfo.h to RISCVBaseInfo.h to be with other TSFlags bits.

Differential Revision: https://reviews.llvm.org/D91114

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[RISCV] Register null target streamer for RISC-V

Summary:
This fixes two llc crashes with the following tests when RISC-V is the default
target.

LLVM :: DebugInfo/Generic/global.ll
LLVM :: DebugInf

[RISCV] Register null target streamer for RISC-V

Summary:
This fixes two llc crashes with the following tests when RISC-V is the default
target.

LLVM :: DebugInfo/Generic/global.ll
LLVM :: DebugInfo/Generic/inlined-strings.ll

Reviewers: HsiangKai

Reviewed By: HsiangKai

Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, sameer.abuasal, apazos, luismarques, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D80352

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[RISCV][AsmParser] Implement .option (no)pic

Differential Revision: https://reviews.llvm.org/D77867

[RISCV] ELF attribute section for RISC-V.

Leverage ARM ELF build attribute section to create ELF attribute section
for RISC-V. Extract the common part of parsing logic for this section
into ELFAttri

[RISCV] ELF attribute section for RISC-V.

Leverage ARM ELF build attribute section to create ELF attribute section
for RISC-V. Extract the common part of parsing logic for this section
into ELFAttributeParser.[cpp|h] and ELFAttributes.[cpp|h].

Differential Revision: https://reviews.llvm.org/D74023

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Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[RISCV] Support .option push and .option pop

This adds support in the RISCVAsmParser the storing of Subtarget feature bits to a stack so that they can be pushed/popped to enable/disable multiple fea

[RISCV] Support .option push and .option pop

This adds support in the RISCVAsmParser the storing of Subtarget feature bits to a stack so that they can be pushed/popped to enable/disable multiple features at once.

Differential Revision: https://reviews.llvm.org/D46424
Patch by Lewis Revill.

llvm-svn: 347774

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[RISCV] Support .option relax and .option norelax

This extends the .option support from D45864 to enable/disable the relax
feature flag from D44886

During parsing of the relax/norelax directives,

[RISCV] Support .option relax and .option norelax

This extends the .option support from D45864 to enable/disable the relax
feature flag from D44886

During parsing of the relax/norelax directives, the RISCV::FeatureRelax
feature bits of the SubtargetInfo stored in the AsmParser are updated
appropriately to reflect whether relaxation is currently enabled in the
parser. When an instruction is parsed, the parser checks if relaxation is
currently enabled and if so, gets a handle to the AsmBackend and sets the
ForceRelocs flag. The AsmBackend uses a combination of the original
RISCV::FeatureRelax feature bits set by e.g -mattr=+/-relax and the
ForceRelocs flag to determine whether to emit relocations for symbol and
branch diffs. Diff relocations should therefore only not be emitted if the
relax flag was not set on the command line and no instruction was ever parsed
in a section with relaxation enabled to ensure correct diffs are emitted.

Differential Revision: https://reviews.llvm.org/D46423
Patch by Lewis Revill.

llvm-svn: 346655

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[RISCV] Support .option rvc and norvc assembler directives

These directives allow the 'C' (compressed) extension to be enabled/disabled
within a single file.

Differential Revision: https://reviews

[RISCV] Support .option rvc and norvc assembler directives

These directives allow the 'C' (compressed) extension to be enabled/disabled
within a single file.

Differential Revision: https://reviews.llvm.org/D45864
Patch by Kito Cheng

llvm-svn: 332107

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[RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamer

llvm-svn: 323507