Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the def

Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (#90267)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation
in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc

This patch changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.

This was reverted with https://github.com/llvm/llvm-project/pull/84597,
because ld.bfd would segfault with unknown riscv attributes. Now that
attributes emission is guarded with a backend flag,
`--riscv-abi-attributes`, this should be safe to reland, since it won't
introduce abi tags unless the user opts into them.

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Reapply "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This patch adds support for the atomic_abi attribute, specifid in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/ris

Reapply "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This patch adds support for the atomic_abi attribute, specifid in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version.

This was previously reverted due to ld.bfd segfaulting w/ unknown riscv
attributes. Attribute emission is now guarded by a backend flag
`--riscv-abi-attributes`, which is off by default. Linker support in
LLD for attribute merging is now in a standalone patch.

Reviewers: kito-cheng, MaskRay, asb

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/90266

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Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This reverts commit 9221f3af8f832d990be986c05d964ad37e5a2356.

As reported
<https://github.com/llvm/llvm-project/pull/84597#issuecommen

Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)"

This reverts commit 9221f3af8f832d990be986c05d964ad37e5a2356.

As reported
<https://github.com/llvm/llvm-project/pull/84597#issuecomment-2079128332>
and confirmed by me locally, adding these attributes causes current GNU
ld to segfault when processing the input. Reverted so we can discuss
the best next step.

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Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)"

This reverts commit 733b271db793ce30c504a1b5c4ae7a8775b0a6a2.

Reverting in order to revert the companion patch a

Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)"

This reverts commit 733b271db793ce30c504a1b5c4ae7a8775b0a6a2.

Reverting in order to revert the companion patch adding the atomics ABI
ELF attributes due to the reported incompatibility with GNU ld.
https://github.com/llvm/llvm-project/pull/84597#issuecomment-2079128332

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[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to

[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)

With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation
in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc

This tag changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.

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[RISCV] Support RISCV Atomics ABI attributes (#84597)

This patch adds support for the `atomic_abi` attribute, specifid in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-el

[RISCV] Support RISCV Atomics ABI attributes (#84597)

This patch adds support for the `atomic_abi` attribute, specifid in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version.

The atomics_abi tag merging is conducted as follows:

- UNKNOWN is safe to merge with all other values.
- A6C is compatible with A6S, and results in the A6C ABI.
- A6C is incompatible with A7, and results in an error.
- A6S and A7 are compatible, and merging results in the A7 ABI.

Note: the A7 is not yet supported in either LLVM or in any current
hardware,
and is therefore ommited from attribute generation in
RISCVTargetStreamer.

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[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)

This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow

[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684)

This introduces a new file, RISCVISAUtils.cpp and moves the rest of
RISCVISAInfo to the TargetParser library.

This will allow us to generate part of RISCVISAInfo.cpp using tablegen.

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[RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)

Instead of caching STI in the RISCVELFTargetStreamer, store the two
flags we need from it.

My goal is to allo

[RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)

Instead of caching STI in the RISCVELFTargetStreamer, store the two
flags we need from it.

My goal is to allow RISCVAsmPrinter to override these flags using IR
module metadata for LTO. So they need to be separated from the STI used
to construct the TargetStreamer.

This patch should be NFC as long as no one is changing the contents of
the STI that was used to construct the TargetStreamer between the
constructor and the use of the flags.

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[RISCV] Remove StackAlign attribute enum. NFC (#79946)

The alignment is directly encoded in the attribute. There doesn't seem
to be a good reason to give the possible alignments a name.

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.

The differences between

[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.

The differences between `RVE` and `RVI` are:
* `RVE` reduces the integer register count to 16(x0-x16).
* The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits.

`RVE` can be combined with all current standard extensions.

The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:
* Only 6 integer argument registers (rather than 8).
* Only 2 callee-saved registers (rather than 12).
* A Stack Alignment of 32bits (rather than 128bits).
* ilp32e isn't compatible with D ISA extension.

If `ilp32e` or `lp64` is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.

To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.

FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.

Differential Revision: https://reviews.llvm.org/D70401

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[RISCV] Rework .option arch target streamer interface

The current interface requires some rather ugly tracking of state due to
splitting up the calls for each argument. Instead, pack them all into a

[RISCV] Rework .option arch target streamer interface

The current interface requires some rather ugly tracking of state due to
splitting up the calls for each argument. Instead, pack them all into a
single call by passing an ArrayRef. Also clean up the dodgy whitespace
emitted for the directive whilst here; there was a stray space between
the tab and .option, and there was a tab rather than a space after the
first comma for some strange reason.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152193

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[RISCV] Merge emitDirectiveOptionArchPlus and emitDirectiveOptionArchMinus into a single interface. NFC

Probably going to do some other refactors after this, but this one
was easy and clearly reduce

[RISCV] Merge emitDirectiveOptionArchPlus and emitDirectiveOptionArchMinus into a single interface. NFC

Probably going to do some other refactors after this, but this one
was easy and clearly reduces duplicate code.

Reviewed By: StephenFan

Differential Revision: https://reviews.llvm.org/D151771

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[RISCV] Support '.option arch' directive

The proposal of '.option arch' directive is https://github.com/riscv-non-isa/riscv-asm-manual/pull/67

Note: For '.option arch, +/-' directive, version numbe

[RISCV] Support '.option arch' directive

The proposal of '.option arch' directive is https://github.com/riscv-non-isa/riscv-asm-manual/pull/67

Note: For '.option arch, +/-' directive, version number is not yet supported.

Reviewed By: luismarques, craig.topper

Differential Revision: https://reviews.llvm.org/D123515

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[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget

This adds an option to emit the command line -mattr/-march into the
attributes of an object file. This c

[RISCV] Add an option to emit the Tag_RISCV_arch attribute based on the assembler's subtarget

This adds an option to emit the command line -mattr/-march into the
attributes of an object file. This can be useful to get objdump to
disassemble instructions that aren't in the base without forcing
users to add a .attribute to the assembly file.

The binutils assembler does this by default.

Similar option exists for ARM. I will wire it to a clang option in
another patch. Similar to https://reviews.llvm.org/D31813

Reviewed By: asb, kito-cheng

Differential Revision: https://reviews.llvm.org/D148782

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV][MC] Add support for RV64E

Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570

[RISCV] Emit .variant_cc directives for vector function calls.

The patch is splitted from D103435. The patch emits .variant_cc [0] for those
function calls that have vector arguments or vector retur

[RISCV] Emit .variant_cc directives for vector function calls.

The patch is splitted from D103435. The patch emits .variant_cc [0] for those
function calls that have vector arguments or vector return values.

[0]: https://github.com/riscv/riscv-elf-psabi-doc/pull/190

Initial authored by: HsiangKai

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D139414

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[RISCV] Support .variant_cc directive for the assembler.

The patch is split from D103435. The patch supported a new directive .variant_cc
that annotates function with STO_RISCV_VARIANT_CC. Symbols m

[RISCV] Support .variant_cc directive for the assembler.

The patch is split from D103435. The patch supported a new directive .variant_cc
that annotates function with STO_RISCV_VARIANT_CC. Symbols marked with
STO_RISCV_VARIANT_CC do not use standard calling conversion or use parameter not
passed in GPR/FPR.

Related: https://github.com/riscv/riscv-elf-psabi-doc/pull/190

Initial authored by: HsiangKai

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D138352

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[RISCV] Fix state persistence bugs (PR55548)

We didn't implement RISCVELFStreamer::reset and cause some very strange
section output for attribute section...just reference D15950 to see how
ARM imple

[RISCV] Fix state persistence bugs (PR55548)

We didn't implement RISCVELFStreamer::reset and cause some very strange
section output for attribute section...just reference D15950 to see how
ARM implement that.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D125905

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[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute

In the past, when construct RISCVAsmBackend, MCTargetOptions.ABIName would be passed and stored in RISCVAsmBackend.
But MCT

[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute

In the past, when construct RISCVAsmBackend, MCTargetOptions.ABIName would be passed and stored in RISCVAsmBackend.
But MCTargetOptions.ABIName can only be specified by -target-abi xxx in command line, if the .ll file has target-abi attribute, the codegen module will ignore it. And the generated object file would have incorrect EFlags value.

https://github.com/llvm/llvm-project/issues/50591 also caused by this problem.

This patch override the AsmPrinter::emitFunctionEntryLabel function and use it to set the target abi value that get from .ll file's target-abi attribute. And storing the target-abi in RISCVTargetStreamer instead of RISCVAsmBackend.

Differential Revision: https://reviews.llvm.org/D121183

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[RISCV] Replace llvm_unreachable with report_fatal_error.

Parsing errors aren't handled earlier in all cases. A simple
example is llc -mtriple=riscv64 -mattr=+zve32f. If F or Finx is
not also specif

[RISCV] Replace llvm_unreachable with report_fatal_error.

Parsing errors aren't handled earlier in all cases. A simple
example is llc -mtriple=riscv64 -mattr=+zve32f. If F or Finx is
not also specified, this will hit a parse error.

Use a fatal_error so that the error is conveyed to the user.

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[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://

[RISCV][NFC] Refactor RISCVISAInfo.

1. Remove computeDefaultABIFromArch and add computeDefaultABI in
RISCVISAInfo.
2. Add parseFeatureBits which may used in D118333.

Differential Revision: https://reviews.llvm.org/D119250

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[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeat

[RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

How many place you need to modify when implementing a new extension for RISC-V?

At least 7 places as I know:

- Add new SubtargetFeature at RISCV.td
- -march parser in RISCV.cpp
- RISCVTargetInfo::initFeatureMap@RISCV.cpp for handling feature vector.
- RISCVTargetInfo::getTargetDefines@RISCV.cpp for pre-define marco.
- Arch string parser for ELF attribute in RISCVAsmParser.cpp
- ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in
canonical order...
- ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in
canonical order...

And now, this patch provide an unified infrastructure for handling (almost)
everything of RISC-V arch string.

After this patch, you only need to update 2 places for implement an extension
for RISC-V:
- Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid.
- Add new entry to RISCVSupportedExtension@RISCVISAInfo.cpp or
SupportedExperimentalExtensions@RISCVISAInfo.cpp .

Most codes are come from existing -march parser, but with few new feature/bug
fixes:
- Accept version for -march, e.g. -march=rv32i2p0.
- Reject version info with `p` but without minor version number like `rv32i2p`.

Differential Revision: https://reviews.llvm.org/D105168

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[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tes

[RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

I've removed the Zbs W instructions that are not part of the frozen spec.

References to B as an extension name have been removed. Tests are updated or split accordingly.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D110669

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[RISCV] Remove experimental-b extension that includes all Zb* extensions

At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ra

[RISCV] Remove experimental-b extension that includes all Zb* extensions

At this point it looks like a B extension will never exist. Instead
Zba, Zbb, Zbc, and Zbs are individual extensions being ratified
together as a package. Unknown at this time when or if the other
Zb* extensions will be ratified.

This patch removes references to the B extension. I've updated and
split tests accordingly.

This has been split from D110669 to make review a little easier.

Differential Revision: https://reviews.llvm.org/D111338

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