[RISCV][NFCI] Rationalize Immediate Definitions (#120718)

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

This MR fixes failed test `CodeGen/RISCV/compress-opt-select.ll`.

It was failed due to previously merged commit `[

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

This MR fixes failed test `CodeGen/RISCV/compress-opt-select.ll`.

It was failed due to previously merged commit `[TTI][RISCV]
Unconditionally break critical edges to sink ADDI (PR #108889)`.

So, regenerated `compress-opt-select` test.

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Revert "[RISCV] Implement tail call optimization in machine outliner" (#117710)

Reverts llvm/llvm-project#115297
Bots are broken

[RISCV] Implement tail call optimization in machine outliner (#115297)

Following up issue #89822, this patch adds opportunity to use tail call
in machine outliner pass.
Also it enables outline pat

[RISCV] Implement tail call optimization in machine outliner (#115297)

Following up issue #89822, this patch adds opportunity to use tail call
in machine outliner pass.
Also it enables outline patterns with X5(T0) register.

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[RISCV] Remove unused includes (NFC) (#115814)

Identified with misc-include-cleaner.

[RISCV][MC] Fix >32bit .insn Directives (#111878)

The original patch had a reasonably significant bug. You could not use
`.insn` to assemble encodings that had any bits set above the low 32
bits.

[RISCV][MC] Fix >32bit .insn Directives (#111878)

The original patch had a reasonably significant bug. You could not use
`.insn` to assemble encodings that had any bits set above the low 32
bits. This is due to the fact that `getMachineOpValue` was truncating
the immediate value, and I did not commit enough tests of useful cases.

This changes the result of `getMachineOpValue` to be able to return the
48-bit and 64-bit immediates needed for the wider `.insn` directives.

I took the opportunity to move some of the test cases around in the file
to make looking at the output of `llvm-objdump` a little clearer.

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[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

This adds `.insn` support for assembling instructions of 48- and
64-bits (only when giving an explicit length). Disassembly alre

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

This adds `.insn` support for assembling instructions of 48- and
64-bits (only when giving an explicit length). Disassembly already
knows to bunch up the instruction bits for these instructions.

This changes some error messages so they are a little clearer.

Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>

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[RISCV] Don't delete all fixups in RISCVMCCodeEmitter::expandLongCondBr. (#109513)

The Fixups vector passed into this function may already have fixups in
it from earlier instructions. We should not

[RISCV] Don't delete all fixups in RISCVMCCodeEmitter::expandLongCondBr. (#109513)

The Fixups vector passed into this function may already have fixups in
it from earlier instructions. We should not erase those. We just want to
erase fixups added by this function.

Fixes #108612.

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[RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.

This dropped the upper 32 bits of the immediate, but I'm not sure
it is ever non-zero.

[RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp. (#89014)

PseudoTail should be a software guarded branch in Ziciflp, since its
branch target is known in link time. JALR/C.JR/C.JALR with

[RISCV] Expand PseudoTAIL with t2 instead of t1 for Zicfilp. (#89014)

PseudoTail should be a software guarded branch in Ziciflp, since its
branch target is known in link time. JALR/C.JR/C.JALR with rs1 as t2 is
termed a software guarded branch. Such branches do not need to land on a
lpad instruction.

ABI Change PR: https://github.com/riscv-non-isa/riscv-asm-manual/pull/93

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[RISCV] Support TLSDESC in the RISC-V backend (#66915)

This patch adds basic TLSDESC support in the RISC-V backend.

Specifically, we add new relocation types for TLSDESC, as prescribed in
https

[RISCV] Support TLSDESC in the RISC-V backend (#66915)

This patch adds basic TLSDESC support in the RISC-V backend.

Specifically, we add new relocation types for TLSDESC, as prescribed in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373, and add a
new pseudo instruction to simplify code generation.

This patch does not try to optimize the local dynamic case, which can be
improved in separate patches.

Linker side changes will also be handled separately.

The current implementation is only enabled when passing the new
`-enable-tlsdesc` codegen flag.

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[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.

[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824

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Use llvm::endianness::{big,little,native} (NFC)

Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces suppo

Use llvm::endianness::{big,little,native} (NFC)

Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces support::{big,little,native} with
llvm::endianness::{big,little,native}.

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[RISCV][MC]Add support for Binary MCExpr

There is an issue: https://github.com/llvm/llvm-project/issues/64612
This issue happens because in RISCVMCCodeEmitter::getImmOpValue it only handles MCExpr k

[RISCV][MC]Add support for Binary MCExpr

There is an issue: https://github.com/llvm/llvm-project/issues/64612
This issue happens because in RISCVMCCodeEmitter::getImmOpValue it only handles MCExpr kind Target and SymbolRef.
When code with format like .+ comes in, it comes with MCExpr kind Binary, the fixupkind remains fixup_riscv_invalid and reports error.

This patch make MCExpr kind Binary handled with the same way as MCExpr kind SymbolRef,
so code with binary expression can get correct fixupkind and be used to generate more complex relocation.

Differential Revision: https://reviews.llvm.org/D157694

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[RISCV] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

Similar to AArch64,AVR,PowerPC: 9e2d100e5322c52e29280c96bbb5609ca5af1539.

[RISCV] Allow LI with symbol difference as constant

This patch lets the assembler accept code like the following:

.Lbuf: ...
.set .Lbuf_len, . - .Lbuf
li a0, .Lbuf_len

It works by translating such

[RISCV] Allow LI with symbol difference as constant

This patch lets the assembler accept code like the following:

.Lbuf: ...
.set .Lbuf_len, . - .Lbuf
li a0, .Lbuf_len

It works by translating such instances of LI into an ADDI and inserting
the correct constant value via a new fixup.

Note that this means that the constant value is restricted to 12 bits
since we cannot insert new instructions during the relaxation stage.
Binutils seems to have the same restriction though.

This patch also fixes a small issue where the SMLoc of an LI wasn't
propagated when translated to ADDI. While this is technically unrelated
to the main functionality of this patch, it improves error messages
related to the new use of LI.

This patch does _not_ allow I-type instructions to take such symbolic
constants as well. While technically possible (and allowed by binutils),
it's probably better to implement this in another patch.

Fixes #57461

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D135960

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[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132819

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[RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC

Even for experimental extensions, I think we always include "Std"
in the feature name.

Reviewed By: asb

Differential Revision: https://reviews

[RISCV] Rename FeatureExtZc* to FeatureStdExtZc*. NFC

Even for experimental extensions, I think we always include "Std"
in the feature name.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146997

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC

Rather than using operator[] on getFeatureBits we can use
hasFeature to shorten the code.

Reviewed By: MaskRay

Differential Revision: ht

[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC

Rather than using operator[] on getFeatureBits we can use
hasFeature to shorten the code.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D144300

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[RISCV] MC relaxation for out-of-range conditional branch.

If .L1 is not within +-4KiB range,

convert

```
bge a0, a1, .L1
```

to

```
blt a0, a1, 8
j .L1
```

In this patch, if the symbol is un

[RISCV] MC relaxation for out-of-range conditional branch.

If .L1 is not within +-4KiB range,

convert

```
bge a0, a1, .L1
```

to

```
blt a0, a1, 8
j .L1
```

In this patch, if the symbol is unresolved at assembly time, do not do
this relaxation.

Fix the bug reported in https://bugs.llvm.org/show_bug.cgi?id=47910

Co-authored-by: Hsiangkai Wang

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D108961

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[RISCV] Replace multiple ifs with a switch. NFC

D108961 will add more instructions to this.

[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added

[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Recommitted with some fixes for the leftover MCII variables in release
builds.

Differential Revision: https://reviews.llvm.org/D129506

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Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are givin

Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are giving more warning
than I saw locally. Reverting to fix those issues.

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Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Targ

Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Differential Revision: https://reviews.llvm.org/D129506

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