[RISCV] Reduce size of CSR lookup tables. NFC (#121606)

Instead of storing 3 different names in each row of the table, use a
separate row for each name and use a flag to indicate what type of name

[RISCV] Reduce size of CSR lookup tables. NFC (#121606)

Instead of storing 3 different names in each row of the table, use a
separate row for each name and use a flag to indicate what type of name
it is. The AltName and DeprecatedName weren't used often enough to
justify storing them as a possibility for every register.

This reduces the .rodata size by 27k and reduces the number of dynamic
relocations since we now only need 1 lookup by name function. The lookup
by name function each contained a ~400 entry table of const char*
pointing to constant strings. Each of those requires a dynamic
relocation.

I also capitalized IsRV32Only in the C++ code to match coding
standards.

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[RISCV] Remove unused includes (NFC) (#115814)

Identified with misc-include-cleaner.

[MCInstPrinter] Make printRegName non-const

Similar to printInst. printRegName may change states (e.g. #113834).

[RISCV] Remove unneeded check for NoRegister from RISCVInstPrinter::printRegReg. NFC

The operand should never be NoRegister.

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287)

This PR is a follow-up of PR #96174 which added the framework to resolve
encoding conflicts among vendor s

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287)

This PR is a follow-up of PR #96174 which added the framework to resolve
encoding conflicts among vendor specific CSRs. This PR explicitly
enables this only for the RISCV target.

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[RISCV] Reduce the amount of similar code in RISCVInstPrinter::printRlist. NFC (#92053)

Remove the switch statement and instead do range checks to know which
pieces we need to print.

[RISCV] Use printRegName in RISCVInstPrinter::printRlist. NFC

Instead of hardcoding all of the register name strings.

[RISCV] Remove IsEABI from RISCVZC::getStackAdjBase. (#89177)

The usage of IsEABI was only valid for RV32E. For RV64E, the stack
adjust
base needs to be 32 when ra,s0-s1 are being saved. Since it

[RISCV] Remove IsEABI from RISCVZC::getStackAdjBase. (#89177)

The usage of IsEABI was only valid for RV32E. For RV64E, the stack
adjust
base needs to be 32 when ra,s0-s1 are being saved. Since it takes more
than 16 bytes to save 3 64-bit registers.

The spec lists the rv32e behavior explicitly, but not rv64e. My
assumption is that the only thing that changes with rv64e is which
registers can be used in the register list, but not how the register
list affects the stack_adj_base.

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[RISCV] Check that the stack adjust immediate for cm.push/pop* has the correct sign and is divisible by 16. (#85295)

To do this I've added a new AsmOperand for cm.push to expect a negative
value. W

[RISCV] Check that the stack adjust immediate for cm.push/pop* has the correct sign and is divisible by 16. (#85295)

To do this I've added a new AsmOperand for cm.push to expect a negative
value. We also use that to customize the print function so that we don't
need to detect cm.push opcode to add the negative sign.

I've renamed some places that used Spimm to be StackAdj since that's
what is being parsed. I'm still not about where we should use Spimm or
StackAdj.

I've removed the printSpimm helper function which in one usage printed
the sp[5:4]<<4 value and the other usage printed the full stack
adjustment. There wasn't anything interesting about how it was printed
it just passed the value to the raw_stream. If there was something
special needed, it's unclear whether it would be the same for the two
different usages so I inlined it.

One open question is whether we need to support stack adjustments
expressed as an expression rather than a literal integer.

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[RISCV] Remove XSfcie extension.

This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
S

[RISCV] Remove XSfcie extension.

This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
SiFive Custom Instruction Extension, which is mentioned in the S76
manual, but then elsewhere in the manual says it is not supported
for S76.

LLVM had various instructions and CSRs listed as part of this
extension, but as far as SiFive is concerned, none of them are part
of it. There are no documented extension names for these instructions
and CSRs either externally or internally.

If these are important to LLVM users, I can facilitate creating
extension names for them and have them documented. For now I'm
removing everything.

Unfortunately, these instructions and CSRs are in LLVM 17 so this
is an incompatible change.

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[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)

Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-he

[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)

Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.

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Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (#75561)

Reverts llvm/llvm-project#74053

Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291

Co-aut

Revert "[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format" (#75561)

Reverts llvm/llvm-project#74053

Breaks https://lab.llvm.org/buildbot/#/builders/5/builds/39291

Co-authored-by: Wang Yaduo <wangyaduo@linux.alibaba.com>

Issue #75563

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[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)

Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-he

[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)

Enable the llvm-objdump to disassemble the immediate of RISCV
instruction in hexadecimal format with --print-imm-hex flag.

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[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.

[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824

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[RISCV][MC] Recognise that fcvt.d.s with frm != 0b000 is valid (#67555)

This seems to be an issue common to both GCC and LLVM. There are various
RISC-V FCVT instructions where the frm field makes n

[RISCV][MC] Recognise that fcvt.d.s with frm != 0b000 is valid (#67555)

This seems to be an issue common to both GCC and LLVM. There are various
RISC-V FCVT instructions where the frm field makes no difference to the
output as the result is always exact (e.g. fcvt.d.s, fcvt.s.h,
fcvt.d.h). As with GCC, we always generate a form of these fcvt
instructions where frm=0b000. However, the ISA manual _doesn't_ state
that frm values are invalid, and we should ensure we can accept them.
This patch does so by adding the frm field to fcvt.d.s and adding an
InstAlias so that if no frm is specified, it defaults to rne (0b000).

This patch just corrects fcvt.d.s in order to allow the approach to be
reviewed, before applying it to the other affected instructions.

I haven't added tests to llvm/test/MC/Disassembler/RISCV, because it
doesn't seem necessary to test there in addition to our usual round-trip
tests in llvm/test/MC/RISCV. But feedback is welcome.

Recently added tests ensure that the default `rne` rounding mode is
printed as desired.

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[MC][RISCV] Add assembly syntax highlighting for RISCV (#65853)

This patch adds support for syntax highlighting RISC-V assembly.
Related patch:
AArch64: https://reviews.llvm.org/D159162
X86: http

[MC][RISCV] Add assembly syntax highlighting for RISCV (#65853)

This patch adds support for syntax highlighting RISC-V assembly.
Related patch:
AArch64: https://reviews.llvm.org/D159162
X86: https://reviews.llvm.org/D159241

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[RISCV] Add support for custom CSRs for Sifive S76.

Support for below CSRs is addeed -
1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs

spec:https://sifive.cdn.pr

[RISCV] Add support for custom CSRs for Sifive S76.

Support for below CSRs is addeed -
1. Branch Prediction Mode CSR
2. Feature Disable CSR
3. Power Dial CSR
4. RNMI CSRs

spec:https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

This patch removes AltName field from SysReg class because we are now using
separate class for custom vendor CSRs. Also, all use of AltName have been changed
to DeprecatedName because both were interchangeably used for old names which are
not in use in latest RISCV spec.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153499

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[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132819

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV] Print Zfa fli instruction FP values in a more adaptive way.

Previously, we printed all constants in scientific notation with
6 digits of precision. This is not enough to accurately display
t

[RISCV] Print Zfa fli instruction FP values in a more adaptive way.

Previously, we printed all constants in scientific notation with
6 digits of precision. This is not enough to accurately display
the smallest value, but increasing the precision would be too much
for other values.

This patch prints values with fractional bits using only as many digits as
needed. 1*2^-15 and 1*2^-16 will be printed in scientific notation while
the others are printed without scientific notation. The integer values
are printed with a single 0 after the decimal point.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D145645

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[RISCV] Make getFPImm return a float instead of a uint32_t. NFC

The one caller bitcasted the uint32_t to float anyway.

[RISCV][MC] Add FLI instruction support for the experimental zfa extension

This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manu

[RISCV][MC] Add FLI instruction support for the experimental zfa extension

This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds assembly support for load-immediate instructions (fli.s/fli.d/fli.h). The assembly prefers decimal constants in C-like syntax. In my implementation, an integer encoding ranging from 0 to 31 can also be accepted, but for the MCInst printer, the constant is specified in decimal notation by default.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140460

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[RISCV] Handle FRMArg as an optional operand instead of using InstAliases.

Instead of having InstAliases without operand. Use the optional
operand infrastructure.

Still use the PrintAliases/NoAlias

[RISCV] Handle FRMArg as an optional operand instead of using InstAliases.

Instead of having InstAliases without operand. Use the optional
operand infrastructure.

Still use the PrintAliases/NoAlias controls to determine if we
print "dyn" or not.

Differential Revision: https://reviews.llvm.org/D142959

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[RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo

We have several usages of compressInst/uncompressInst in different
files, which results in duplicated code. We move their implementatio

[RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo

We have several usages of compressInst/uncompressInst in different
files, which results in duplicated code. We move their implementations
to RISCVBaseInfo under namespace RISCVRVC to remove these duplications.

Reviewed By: craig.topper, asb

Differential Revision: https://reviews.llvm.org/D141897

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[RISCV] Remove MCRegisterInfo dependency from compressInst/uncompresInst/isCompressibleInst.

This was being used to lookup the register class for a register number,
but those live in a tablegened ar

[RISCV] Remove MCRegisterInfo dependency from compressInst/uncompresInst/isCompressibleInst.

This was being used to lookup the register class for a register number,
but those live in a tablegened array. We can index that array directly
just like RISCVAsmParser does.

Differential Revision: https://reviews.llvm.org/D141951

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