[RISCV] Remove unused includes (NFC) (#115814)

Identified with misc-include-cleaner.

[MC] Forward declare ELFObjectWriter (#100989)

[RISCV] Create mapping symbols with non-unique names

Similar to #99836 for AArch64.

Non-unique names save .strtab space and match GNU assembler.

Pull Request: https://github.com/llvm/llvm-project/

[RISCV] Create mapping symbols with non-unique names

Similar to #99836 for AArch64.

Non-unique names save .strtab space and match GNU assembler.

Pull Request: https://github.com/llvm/llvm-project/pull/99903

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MCAssmembler: Move ELFHeaderEFlags to ELFObjectWriter

Now that MCELFStreamer can access ELFObjectWriter (commit
70c52b62c5669993e341664a63bfbe5245e32884), we can move ELFHeaderEFlags
there.

[MC] Change Subsection parameters from const MCExpr * to uint32_t

Follow-up to 05ba5c0648ae5e80d5afce270495bf3b1eef9af4. uint32_t is
preferred over const MCExpr * in the section stack uses because i

[MC] Change Subsection parameters from const MCExpr * to uint32_t

Follow-up to 05ba5c0648ae5e80d5afce270495bf3b1eef9af4. uint32_t is
preferred over const MCExpr * in the section stack uses because it
should only be evaluated once. Change the paramter type to match.

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[MC] Remove RelaxAll parameters from create*Streamer

Related to clean-up opportunities discussed at #90013.

After these cleanups, the `RelaxAll` parameter from
`createMCObjectStreamer` can be remov

[MC] Remove RelaxAll parameters from create*Streamer

Related to clean-up opportunities discussed at #90013.

After these cleanups, the `RelaxAll` parameter from
`createMCObjectStreamer` can be removed as well. As
`createMCObjectStreamer` is a more user-facing API and used by two files
in mlir/, we postpone the cleanup to the future.

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[MC] Move setRelaxAll() calls to MCObjectStreamer

Related to clean-up opportunities discussed at #90013.

[RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)

Instead of caching STI in the RISCVELFTargetStreamer, store the two
flags we need from it.

My goal is to allo

[RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)

Instead of caching STI in the RISCVELFTargetStreamer, store the two
flags we need from it.

My goal is to allow RISCVAsmPrinter to override these flags using IR
module metadata for LTO. So they need to be separated from the STI used
to construct the TargetStreamer.

This patch should be NFC as long as no one is changing the contents of
the STI that was used to construct the TargetStreamer between the
constructor and the use of the flags.

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[RISCV] Set the RVC bit in the ELF EFlags for C or Zca. (#80913)

[RISCV] Force relocations if initial MCSubtargetInfo contains FeatureRelax (#77436)

Regarding
```
.option norelax
j label
.option relax
// relaxable instructions
// For assembly input, RISCVAs

[RISCV] Force relocations if initial MCSubtargetInfo contains FeatureRelax (#77436)

Regarding
```
.option norelax
j label
.option relax
// relaxable instructions
// For assembly input, RISCVAsmParser::ParseInstruction will set ForceRelocs (https://reviews.llvm.org/D46423).
// For direct object emission, ForceRelocs is not set after https://github.com/llvm/llvm-project/pull/73721
label:
```

The J instruction needs a relocation to ensure the target is correct
after linker relaxation. This is related a limitation in the assembler:
RISCVAsmBackend::shouldForceRelocation decides upfront whether a
relocation is needed, instead of checking more information (whether
there are relaxable fragments in between).

Despite the limitation, `j label` produces a relocation in direct object
emission mode, but was broken by #73721 due to the shouldForceRelocation
limitation.

Add a workaround to RISCVTargetELFStreamer to emulate the previous
behavior.

Link: https://github.com/ClangBuiltLinux/linux/issues/1965

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[RISCV][MC] Implement mapping symbols

Mapping symbols [1] are special ELF symbols that can be inserted to
indicate regions of code or data. A sequence of data bytes is indicated
by a `$d` (or `$d.<a

[RISCV][MC] Implement mapping symbols

Mapping symbols [1] are special ELF symbols that can be inserted to
indicate regions of code or data. A sequence of data bytes is indicated
by a `$d` (or `$d.<any>`) symbol pointing to its start while a sequence
of instructions uses a `$x` (or `$x.<any>`) symbol. This can be used,
for example, to assist disassembling a memory region containing both
data and code.

This patch implements mapping symbols for RISC-V, copying the
implementation mostly from the AArch64 target.

Note that the `$x<ISA>` mapping symbol, indicating an instruction
sequence with a specific ISA extension, is not implemented by this
patch. As far as I can tell, binutils doesn't implement this yet either.

Note that this patch uses the same symbol naming convention as the
AArch64 target: always use `$x.i` and `$d.i` (where `i` is a
monotonically increasing counter). This differs from binutils where all
symbols are named `$x` or `$d` (causing multiple symbol having the same
name). I'm not not sure whether it makes more sense to avoid duplicate
symbol names or be consistent with binutils.

Note that the handling of nop-slides inserted for alignment differs from
binutils: binutils always marks the nops as instructions (`$x`) while
this patch doesn't insert a symbol for the nops (so the last inserted
symbol is used). I believe binutil's behavior makes most sense but this
seems difficult to implement in LLVM as the insertion of nops is handled
by `RISCVAsmBackend`. At this point, inserting ELF symbols seems
impossible. Any ideas for how to handle this would be appreciated.

[1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#mapping-symbol

Depends on D156190 and D156236

Differential Revision: https://reviews.llvm.org/D153260

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[RISCV] Allow delayed decision for ADD/SUB relocations

For a label difference `A-B` in assembly, if A and B are separated by a
linker-relaxable instruction, we should emit a pair of ADD/SUB
relocati

[RISCV] Allow delayed decision for ADD/SUB relocations

For a label difference `A-B` in assembly, if A and B are separated by a
linker-relaxable instruction, we should emit a pair of ADD/SUB
relocations (e.g. R_RISCV_ADD32/R_RISCV_SUB32,
R_RISCV_ADD64/R_RISCV_SUB64).

However, the decision is made upfront at parsing time with inadequate
heuristics (`requiresFixup`). As a result, LLVM integrated assembler
incorrectly suppresses R_RISCV_ADD32/R_RISCV_SUB32 for the following
code:
```
// Simplified from a workaround https://android-review.googlesource.com/c/platform/art/+/2619609
// Both end and begin are not defined yet. We decide ADD/SUB relocations upfront and don't know they will be needed.
.4byte end-begin

begin:
call foo
end:
```

To fix the bug, make two primary changes:

* Delete `requiresFixups` and the overridden emitValueImpl (from D103539).
This deletion requires accurate evaluateAsAbolute (D153097).
* In MCAssembler::evaluateFixup, call handleAddSubRelocations to emit
ADD/SUB relocations.

However, there is a remaining issue in
MCExpr.cpp:AttemptToFoldSymbolOffsetDifference. With MCAsmLayout, we may
incorrectly fold A-B even when A and B are separated by a
linker-relaxable instruction. This deficiency is acknowledged (see
D153097), but was previously bypassed by eagerly emitting ADD/SUB using
`requiresFixups`. To address this, we partially reintroduce `canFold` (from
D61584, removed by D103539).

Some expressions (e.g. .size and .fill) need to take the `MCAsmLayout`
code path in AttemptToFoldSymbolOffsetDifference, avoiding relocations
(weird, but matching GNU assembler and needed to match user
expectation). Switch to evaluateKnownAbsolute to leverage the `InSet`
condition.

As a bonus, this change allows for the removal of some relocations for
the FDE `address_range` field in the .eh_frame section.

riscv64-64b-pcrel.s contains the main test.
Add a linker relaxable instruction to dwarf-riscv-relocs.ll to test what
it intends to test.
Merge fixups-relax-diff.ll into fixups-diff.ll.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D155357

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[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

[RISCV] Replace RISCV -> RISC-V in comments. NFC

To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449

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[RISCV][MC] Add support for RV64E

Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570

[RISCV][MC] Adjust conditions to emit R_RISCV_ADD*/R_RISCV_SUB* pairs

D132262 tried to simplify `IsMetadataOrEHFrameSection` originally introduced in
D127549 but caused a regression as `.quad` direc

[RISCV][MC] Adjust conditions to emit R_RISCV_ADD*/R_RISCV_SUB* pairs

D132262 tried to simplify `IsMetadataOrEHFrameSection` originally introduced in
D127549 but caused a regression as `.quad` directives in

```
.section .note,"a",@note; note:
.quad extern-note # extern is undefined

.section .rodata,"a",@progbits; rodata:
.quad extern-rodata # extern is undefined

.section .nonalloc,"",@progbits; nw:
.quad extern-nw
```

are incorrectly rejected: these differences may be link-time constants and
are allowed in GNU assembler and LLVM MC's non-RISC-V ports.

Relax the conditions to allow these cases. For A-B, A may be defined later, but
this requiresFixups call has to eagerly make a decision. For now, emit ADD/SUB
unless A is `.L*`. This euristic handles many temporary label differences for
.debug_* and .apple_types sections. Ideally we should delay the decision of
PC-relative vs ADD/SUB until A is defined.

Reviewed By: compnerd

Differential Revision: https://reviews.llvm.org/D145474

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[RISCV] A@plt-B+C: emit R_RISCV_PLT32 even if A is defined

Follow-up to D143226

Currently we incorrectly emit R_RISCV_ADD32/R_RISCV_SUB32.
Emit R_RISCV_PLT32 instead. The new behavior matches x86-6

[RISCV] A@plt-B+C: emit R_RISCV_PLT32 even if A is defined

Follow-up to D143226

Currently we incorrectly emit R_RISCV_ADD32/R_RISCV_SUB32.
Emit R_RISCV_PLT32 instead. The new behavior matches x86-64 and AArch64.

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[RISCV][NFCI] Use common MCELFStreamer code for attribute emission

D102894 introduced common code for the emission of ELF attributes. Our
implementation in RISC-V predates this, and basically copies

[RISCV][NFCI] Use common MCELFStreamer code for attribute emission

D102894 introduced common code for the emission of ELF attributes. Our
implementation in RISC-V predates this, and basically copies the Arm
logic at the time. This patch removes that duplication and uses the
shared logic instead.

Differential Revision: https://reviews.llvm.org/D145570

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[RISCV] Move RISCVELFStreamer::getRelocPairForSize to RISCVFixUpKinds.h and reuse it. NFC

Reuse it for RISCVAsmBackend.cpp.
While there make the function return a pair of MCFixupKind to
remove stati

[RISCV] Move RISCVELFStreamer::getRelocPairForSize to RISCVFixUpKinds.h and reuse it. NFC

Reuse it for RISCVAsmBackend.cpp.
While there make the function return a pair of MCFixupKind to
remove static_casts elsewhere.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D142955

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[RISCV] Change the return type of getStreamer() to support the use of overloading and other functions in RISCVELFStreamer

Move the declaration of RISCVELFStreamer from RISCVELFStreamer.cpp to RISCVE

[RISCV] Change the return type of getStreamer() to support the use of overloading and other functions in RISCVELFStreamer

Move the declaration of RISCVELFStreamer from RISCVELFStreamer.cpp to RISCVELFStreamer.h.
Change the return type of getStreamer() to support the use of overloading and other functions in RISCVELFStreamer.

Differential Revision: https://reviews.llvm.org/D138500

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[RISCV] Support .variant_cc directive for the assembler.

The patch is split from D103435. The patch supported a new directive .variant_cc
that annotates function with STO_RISCV_VARIANT_CC. Symbols m

[RISCV] Support .variant_cc directive for the assembler.

The patch is split from D103435. The patch supported a new directive .variant_cc
that annotates function with STO_RISCV_VARIANT_CC. Symbols marked with
STO_RISCV_VARIANT_CC do not use standard calling conversion or use parameter not
passed in GPR/FPR.

Related: https://github.com/riscv/riscv-elf-psabi-doc/pull/190

Initial authored by: HsiangKai

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D138352

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RISCV: adjust relocation emission

Simplify and make the pair-wise relocation more precise. If either of
the symbol references are textual, the relocation must be delayed. If
the difference is acro

RISCV: adjust relocation emission

Simplify and make the pair-wise relocation more precise. If either of
the symbol references are textual, the relocation must be delayed. If
the difference is across sections, delay it as well which partially
matches the behaviour of gas. We unfortunately do not handle the case
where the difference references a symbol that is not yet defined. In
such a case, we simply fail to resolve the difference, which should
hopefully not be too onerous (particularly since no other target
supports cross-section references and it is not clear if this was
intentional on the part of RISCV).

Differential Revision: https://reviews.llvm.org/D132262
Reviewed By: @MaskRay

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[RISCV][MC] Add minimal support for Ztso extension

This is a minimalist implementation which simply adds the extension (in the experimental namespace since its not ratified), and wires up the settin

[RISCV][MC] Add minimal support for Ztso extension

This is a minimalist implementation which simply adds the extension (in the experimental namespace since its not ratified), and wires up the setting of the required ELF header flag. Future changes will include codegen changes to exploit the stronger memory model.

This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.

Differential Revision: https://reviews.llvm.org/D133239

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[MC][RISCV] Suppress R_RISCV_{ADD,SUB}32 in .apple_names .apple_types after D127549

This fixes test/DebugInfo/Generic/accel-table-hash-collisions.ll and
cross-cu-inlining.ll when the default triple

[MC][RISCV] Suppress R_RISCV_{ADD,SUB}32 in .apple_names .apple_types after D127549

This fixes test/DebugInfo/Generic/accel-table-hash-collisions.ll and
cross-cu-inlining.ll when the default triple is riscv. llvm-dwarfdump
--apple-names does not resolve R_RISCV_{ADD,SUB}32 in .apple_names .apple_types
and having ADD/SUB will cause decoding failure `Atom[0]: Error extracting the
value`.

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RISCV: handle 64-bit PCREL data relocations

We would previously fail to handle 64-bit PC-relative relocations on
RISCV. This was exposed by trying to build with
`-fprofile-instr-generate`.

The ori

RISCV: handle 64-bit PCREL data relocations

We would previously fail to handle 64-bit PC-relative relocations on
RISCV. This was exposed by trying to build with
`-fprofile-instr-generate`.

The original changes restricted the relocation handling to the text
segment as the paired relocations are undesirable in at least the debug
and .eh_frame sections. We now make this explicit to handle the general
case for the data relocations as well.

It would be preferable to use `R_RISCV_n_PCREL` when available to avoid
an extra relocation.

Differential Revision: https://reviews.llvm.org/D127549
Reviewed By: luismarques, MaskRay

Fixes: #55971

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[MC] De-capitalize SwitchSection. NFC

Add SwitchSection to return switchSection. The API will be removed soon.