| #
d421c5f8 |
| 05-May-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Directly create MCOperands from addImplySP in Disassembler. NFC
Instead of passing a constant to DecodeGPRRegisterClass, just create
the X2 register directly.
|
|
Revision tags: llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
|
| #
0b9a620b |
| 15-Apr-2022 |
Nelson Chu <nelson.chu@sifive.com> |
[RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
Differential Revision: https:/
[RISCV] Support assembler and dis-assembler for VCIX extension.
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
Differential Revision: https://reviews.llvm.org/D144530
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|
| #
29463612 |
| 27-Mar-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.
[RISCV] Replace RISCV -> RISC-V in comments. NFC
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.
More patches will follow.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D146449
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|
| #
c39dd7c1 |
| 23-Mar-2023 |
Job Noorman <jnoorman@igalia.com> |
[RISCV][MC] Add support for RV64E
Implement MC support for the recently ratified RV64E base instruction
set.
Differential Revision: https://reviews.llvm.org/D143570
|
| #
f68f04d0 |
| 24-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
in
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144681
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|
| #
7b79e8d4 |
| 23-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds ind
[RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20
Depends on D144249
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144647
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|
| #
f6262201 |
| 23-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b
Depends on D144002
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144249
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|
| #
16a6cf6a |
| 22-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core
[RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd
Depends on D144496
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144501
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|
| #
f5b484c5 |
| 22-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache manage
[RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144496
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|
| #
bbb58a23 |
| 21-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GP
[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd
Depends on D143847
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D144002
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|
| #
34aff475 |
| 17-Feb-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC
Rather than using operator[] on getFeatureBits we can use
hasFeature to shorten the code.
Reviewed By: MaskRay
Differential Revision: ht
[RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC
Rather than using operator[] on getFeatureBits we can use
hasFeature to shorten the code.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D144300
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|
| #
16a66af0 |
| 17-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension"
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
|
| #
d2918544 |
| 13-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GP
[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd
Depends on D143847
Differential Revision: https://reviews.llvm.org/D144002
show more ...
|
| #
d4012bc4 |
| 14-Feb-2023 |
Manolis Tsamis <manolis.tsamis@vrull.eu> |
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate
[RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for this
extension is available at:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154
Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143847
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|
| #
fc02eeb2 |
| 13-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewha
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143036
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143439
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|
| #
04a2baf5 |
| 13-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs. It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBs is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143036
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|
| #
0bda1992 |
| 08-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"
This reverts commit 656188ddc4075eb50260607b3497589873f373d2.
|
| #
b0c31322 |
| 08-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"
This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.
|
| #
19a59099 |
| 31-Jan-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewha
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.
It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBb is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143036
Differential Revision: https://reviews.llvm.org/D143439
show more ...
|
| #
656188dd |
| 30-Jan-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs. It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBs is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Depends on D143394
Differential Revision: https://reviews.llvm.org/D143036
show more ...
|
| #
e25b30d9 |
| 08-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba. It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.
The current (as of this commit) public documentation for XTHeadBa is
available from:
https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf
Support for these instructions has already landed in GNU Binutils:
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D143029
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|
| #
c7449c17 |
| 07-Feb-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC
For 4 byte instructions we were always setting size to 4 eventually. Same
for 2 byte instructions. So do it as soon as
[RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC
For 4 byte instructions we were always setting size to 4 eventually. Same
for 2 byte instructions. So do it as soon as we know the from the opcode.
Add a return to the end of the 4 byte code so we don't have to have an else
around the 2 byte code.
Differential Revision: https://reviews.llvm.org/D143445
show more ...
|
| #
2398e205 |
| 06-Feb-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Remove DecoderMethod from C_NOP_HINT. NFC
This doesn't appear to be needed.
Differential Revision: https://reviews.llvm.org/D143367
|
| #
ba8b8a73 |
| 04-Feb-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
[RISCV][NFC] Update debug message for XTHeadVdot
As we prepare the tree to add more vendor-defined extensions that are
originating with T-Head, the debug message announcing the XTheadVdot
decoder na
[RISCV][NFC] Update debug message for XTHeadVdot
As we prepare the tree to add more vendor-defined extensions that are
originating with T-Head, the debug message announcing the XTheadVdot
decoder namespace should refer to XTHeadVdot instead of all T-Head
custom extensions.
show more ...
|
| #
3a606785 |
| 06-Feb-2023 |
Craig Topper <craig.topper@sifive.com> |
[RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC
The tablegen generated code is templated based on the type of Insn
passed to decodeInstruction which is c
[RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC
The tablegen generated code is templated based on the type of Insn
passed to decodeInstruction which is currently uint32_t. All of the
fields extracted will this type.
show more ...
|