[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/produc

[RISCV] Add MIPS extensions (#121394)

Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)

The official product page here:
https://mips.com/products/hardware/p8700

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[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)

Previously we used a fixed assembly string as well as encoding for the
carry-in vector mask, since it will always be there. However, th

[RISCV][MC] Create an AsmOperand for carry-in vmask (#124317)

Previously we used a fixed assembly string as well as encoding for the
carry-in vector mask, since it will always be there. However, this makes
both AsmParser and disassembler to either create a garbage MCOperand for
the mask or fail to add one as a whole. This wouldn't be a problem for
majority of the cases but tools like llvm-mca who relies on MCInst will
fail to account for the register dependency on these mask operands.

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[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/r

[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881)

This extension adds eight 48 bit load store instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/

[RISCV] Add Qualcomm uC Xqciint (Interrupts) extension (#122256)

This extension adds eleven instructions to accelerate interrupt
servicing.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicm (Conditional Move) extension (#121752)

The Qualcomm uC Xqcicm extension adds 13 conditional move instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:

[RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292)

This extension adds 12 instructions that conditionally load an immediate
value.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found a

[RISCV] Add Qualcomm uC Xqciac (Load-Store Adress calculation) extension (#121037)

This extension adds 3 instructions that perform load-store address
calculation.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>
Co-authored-by: Sudharsan Veeravalli <quic_svs@quicinc.com>

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[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (#119823)

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.c

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504)

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

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[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/risc

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113)

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
http

[RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987)

This extension adds 8 load/store instructions with a scaled index
addressing mode.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.co

[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)

The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

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[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432)

Fixes 2 old TODOs

[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

If we disassemble other rounding modes, we'll print something that can't
be parsed.

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to on

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

This patches adds a 32 bit register class for use with Zfinx instructions. This makes them more similar to F instructions and allows us to only spill 32 bits.

I've added CodeGenOnly instructions for load/store using GPRF32 as that gave better results than insert_subreg/extract_subreg.

Function arguments use this new GPRF32 register class for f32 arguments with Zfinx. Eliminating the need to use RISCVISD::FMV* nodes.

This is similar to #107446 which adds a 16 bit register class.

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[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

This patches adds a 16 bit register class for use with Zhinx
instructions. This makes them more similar to Zfh instructions and
allows us t

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

This patches adds a 16 bit register class for use with Zhinx
instructions. This makes them more similar to Zfh instructions and
allows us to only spill 16 bits.

I've added CodeGenOnly instructions for load/store using GPRF16 as that
gave better results than insert_subreg/extract_subreg. I'm using FSGNJ
for GPRF16 copy with Zhinx as that gave better results. Zhinxmin will
use ADDI+subreg operations.

Function arguments use this new GPRF16 register class for f16 arguments
with Zhinxmin. Eliminating the need to use RISCVISD::FMV* nodes.

I plan to extend this idea to Zfinx next.

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[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d aliases.

We were missing test coverage for fneg.d/fabs.d for Zdinx. When I
added it revealed it only worked on RV64. The as

[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d aliases.

We were missing test coverage for fneg.d/fabs.d for Zdinx. When I
added it revealed it only worked on RV64. The assembler was not
creating a GPRPair register class on RV32 so the alias couldn't match.
The disassembler was also not using GPRPair registers preventing the
aliases from printing in disassembly too.

I've fixed the assembler by adding new parsing methods in an attempt
to get decent diagnostics. This is hard since the mnemonics are
ambiguous between D and Zdinx. Tests have been adjusted for some
differences in what errors are reported first.

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[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.

These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.

As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.

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[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)

We don't have any instructions defined yet, but that we can still read the correct number of bytes when disassembling. This

[RISCV] Support instruction sizes up to 176-bits in disassembler. (#90371)

We don't have any instructions defined yet, but that we can still read the correct number of bytes when disassembling. This should better match GNU objdump behavior.

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[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. (#90254)

This reduces nesting of the common 32-bit case and makes it easier to
add longer instruction lengths in th

[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. (#90254)

This reduces nesting of the common 32-bit case and makes it easier to
add longer instruction lengths in the future.

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[RISCV] Fix off by 1 typo in decodeVMaskReg. NFC

We're decoding a 1 bit field, but checked that the value was <= 2
instead of <= 1.

This isn't a functional change because the generated disassembler

[RISCV] Fix off by 1 typo in decodeVMaskReg. NFC

We're decoding a 1 bit field, but checked that the value was <= 2
instead of <= 1.

This isn't a functional change because the generated disassembler code
that calls this only extracts 1 bit.

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[RISCV] Consistently use uint32_t in Disassembler decode functions. NFC

We had some uses of uint64_t and unsigned. These all come from tblgen
code that is templated on InsnType which is currently ui

[RISCV] Consistently use uint32_t in Disassembler decode functions. NFC

We had some uses of uint64_t and unsigned. These all come from tblgen
code that is templated on InsnType which is currently uint32_t.

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[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)

Planning to declare all extensions in tablegen so we can generate the
tables for RISCVISAInfo.cpp. This requires making "e" consistent with

[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC (#89174)

Planning to declare all extensions in tablegen so we can generate the
tables for RISCVISAInfo.cpp. This requires making "e" consistent with
other extensions.

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[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896)

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores

[RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896)

These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.

This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally for
some time. It uses XSiFive instead of XSf like the newer extensions.
`cease` did not have an internal extension name so its using the `XSf`
convention.

The spec for the instructions is here
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.

Column width in the extension printing had to be changed to accommodate
a longer extension name.

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[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variable warning. (#80651)