[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418)

This changes the register class to GPRPair and adds the destination
register as a source with a tied operand cons

[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418)

This changes the register class to GPRPair and adds the destination
register as a source with a tied operand constraint.

Parsing for the paired register is done with a custom parser that
checks for even register and converts it to its pair version. A
bit of care needs to be taken so that we only parse as a pair register
based on which instruction we're parsing and the mode in the subtarget.
This allows amocas.w to be parsed correcty in both modes.

I've added a FIXME to note that we should be creating pair registers
for Zdinx on RV32 to match the instructions CodeGen generates.

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[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)

-Rename to GPRPair.
-Rename registers to be named like X10_X11 instead of X10_PD. Except X0
which is now X0_Pair since

[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)

-Rename to GPRPair.
-Rename registers to be named like X10_X11 instead of X10_PD. Except X0
which is now X0_Pair since it is not paired with X1.
-Use unknown size and offset for the subreg indices. This might
be a functional change, but does not affect any lit tests.

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[RISCV] Add MC layer support for Zicfiss. (#66043)

The patch adds the instructions in Zicfiss extension. Zicfiss extension
is to support shadow stack for control flow integrity. This patch is
base

[RISCV] Add MC layer support for Zicfiss. (#66043)

The patch adds the instructions in Zicfiss extension. Zicfiss extension
is to support shadow stack for control flow integrity. This patch is
based on version [0.3.1].

[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1

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[RISCV] Remove XSfcie extension.

This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
S

[RISCV] Remove XSfcie extension.

This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
SiFive Custom Instruction Extension, which is mentioned in the S76
manual, but then elsewhere in the manual says it is not supported
for S76.

LLVM had various instructions and CSRs listed as part of this
extension, but as far as SiFive is concerned, none of them are part
of it. There are no documented extension names for these instructions
and CSRs either externally or internally.

If these are important to LLVM users, I can facilitate creating
extension names for them and have them documented. For now I'm
removing everything.

Unfortunately, these instructions and CSRs are in LLVM 17 so this
is an incompatible change.

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[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)

he spimm operand is an immediate whose only 4-5th bit could be setted
and not based on rlist operand

[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.

[RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824

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[RISCV] Support Xsfvfnrclipxfqf extensions (#68297)

FP32-to-int8 Ranged Clip Instructions

https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf

[RISCV] Support Xsfvfwmaccqqq extensions (#68296)

Bfloat16 Matrix Multiply Accumulate Instruction

https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf

[RISCV][NFC] Simplify vector register decoding methods (#70423)

Combine redundant 'if' statements and simplify 'switch' statements.

[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)

SiFive Int8 Matrix Multiplication Extensions Specification

https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad601125

[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)

SiFive Int8 Matrix Multiplication Extensions Specification

https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf

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[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.

All of them have prefix 'X' in DecoderNamespace.

[RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC

This is consistent with other vendor extensions.

[RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC

[RISCV] Add support for XCVbi extension in CV32E40P

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific exte

[RISCV] Add support for XCVbi extension in CV32E40P

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.

bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412

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Revert "[RISCV] Add support for XCVbi extension in CV32E40P"

This reverts commit bf2ad26b4ff856aab9a62ad168e6bdefeedc374f as it
checked in merge conflict markers.

[RISCV] Add support for XCVbi extension in CV32E40P

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific exte

[RISCV] Add support for XCVbi extension in CV32E40P

Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412

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[RISCV] Add support for XCVsimd extension in CV32E40P

Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific

[RISCV] Add support for XCVsimd extension in CV32E40P

Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153721

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[RISCV] Add support for XCValu extension in CV32E40P

Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific ext

[RISCV] Add support for XCValu extension in CV32E40P

Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153748

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[RISCV] Add support for custom instructions for Sifive S76.

Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE

Additionally, Zihintpause extension is added to sifive s7

[RISCV] Add support for custom instructions for Sifive S76.

Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153370

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[RISCV] Add support for XCVmac extension in CV32E40P

Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specif

[RISCV] Add support for XCVmac extension in CV32E40P

Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152821

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[RISCV] Add support for XCVbitmanip extension in CV32E40P

Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor s

[RISCV] Add support for XCVbitmanip extension in CV32E40P

Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj.

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152915

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[RISCV][NFC] Simplify decoding code of disassembler

The decoding parts are reduplicative, we add a macro to simplify
the code.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://

[RISCV][NFC] Simplify decoding code of disassembler

The decoding parts are reduplicative, we add a macro to simplify
the code.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D151309

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[RISCV] Rework how implied SP operands work in the disassembler. NFC

Previously we added the SP operands when an immediate operand was added
to certain opcodes.

This patch moves it to a post proces

[RISCV] Rework how implied SP operands work in the disassembler. NFC

Previously we added the SP operands when an immediate operand was added
to certain opcodes.

This patch moves it to a post processing step using the information
in MCInstrDesc. This avoids an explicit opcode list in RISCVDisassembler.cpp.

In considered using a custom DecoderMethod, but the bit swizzling we
need to do for the immediates on these instructions made that
unattractive.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D149931

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[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

[RISCV] Add MC support of RISCV zcmp Extension

This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132819

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[RISCV] Add DecoderNamespace to Zcmt instructions.

The Zcmt instructions overlap encoding space with some C extension
instructions. Isolate to a separate namespace.

Reviewed By: VincentWu

Differen

[RISCV] Add DecoderNamespace to Zcmt instructions.

The Zcmt instructions overlap encoding space with some C extension
instructions. Isolate to a separate namespace.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149891

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