[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

#119969 adds a couple of new methods to this class, which will need to
be overridden by these targets.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/119968

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[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)

Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same in

[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)

Utilize common API in PPCTargetParser
(https://github.com/llvm/llvm-project/pull/97541) to set default CPU
with same interfaces for LLC.
This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU
to ppc64.

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[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC

Some targets only pass a TargetMachine & to their subtarget constructor
and require a static_cast to their

[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC

Some targets only pass a TargetMachine & to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.

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[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

Replace it with a forward declaration instead. Analysis.h is pulled in
by all passes, but not all passes need to access the module.

[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-l

[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget->enableSubRegLiveness()`
has been changed to `MRI->subRegLivenessEnabled()` to make sure the
option properly applies.

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[PowerPC] Tune AIX shared library TLS model at function level (#84132)

Under some circumstance (library loaded with the main program), TLS
initial-exec model can be applied to local-dynamic access(

[PowerPC] Tune AIX shared library TLS model at function level (#84132)

Under some circumstance (library loaded with the main program), TLS
initial-exec model can be applied to local-dynamic access(es). We
could use some simple heuristic to decide the update at function level:
* If there is equal or less than a number of TLS local-dynamic access(es)
in the function, use TLS initial-exec model. (the threshold which default to
1 is controlled by hidden option)

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[PowerPC][AIX] Enable aix-small-local-dynamic-tls target attribute (#86641)

Following the aix-small-local-exec-tls target attribute, this patch adds
a target attribute for an AIX-specific option in

[PowerPC][AIX] Enable aix-small-local-dynamic-tls target attribute (#86641)

Following the aix-small-local-exec-tls target attribute, this patch adds
a target attribute for an AIX-specific option in llc that informs the
compiler that it can use a faster access sequence for the local-dynamic
TLS model (formally named aix-small-local-dynamic-tls) when TLS
variables are less than ~32KB in size.

The patch either produces an addi/la with a displacement off of module
handle (return value from .__tls_get_mod) when the address is
calculated, or it produces an addi/la followed by a load/store when the
address is calculated and used for further accesses.

---------

Co-authored-by: Amy Kwan <amy.kwan1@ibm.com>

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[AIX] Support per global code model. (#79202)

Exploit the per global code model attribute on AIX. On AIX we need to
update both the code sequence used to access the global (either 1 or 2
instructi

[AIX] Support per global code model. (#79202)

Exploit the per global code model attribute on AIX. On AIX we need to
update both the code sequence used to access the global (either 1 or 2
instructions for small and large code model respectively) and the
storage mapping class that we emit the toc entry.

---------

Co-authored-by: Amy Kwan <akwan0907@gmail.com>

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[AIX][TOC] Fix buildbot failures from commit b4ae8df (#85303)

The following tests fail when built with Address
and Undefined sanitizers:
CodeGen/PowerPC/basic-toc-data-def.ll
CodeGen/PowerPC/toc-

[AIX][TOC] Fix buildbot failures from commit b4ae8df (#85303)

The following tests fail when built with Address
and Undefined sanitizers:
CodeGen/PowerPC/basic-toc-data-def.ll
CodeGen/PowerPC/toc-data-large-array2.ll

Subtarget may be null in emitGlobalVariable, for example in the testcase
where we have no functions in the IR. The fix moves this function from
PPCSubtarget to a static helper function. This only fails with
sanitizers because the Subtarget is not used in the member function.

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[AIX][TOC] Add -mtocdata/-mno-tocdata options on AIX (#67999)

This patch enables support that the XL compiler had for AIX under
-qdatalocal/-qdataimported.

[NFC] Remove unused parameter from shouldAssumeDSOLocal()

[AIX][TLS] Disallow the use of -maix-small-local-exec-tls and -fno-data-sections (#79252)

This patch disallows the use of the -maix-small-local-exec-tls and
-fno-data-sections options within clang,

[AIX][TLS] Disallow the use of -maix-small-local-exec-tls and -fno-data-sections (#79252)

This patch disallows the use of the -maix-small-local-exec-tls and
-fno-data-sections options within clang, and also disallows the use of
the aix-small-local-exec-tls attribute with the -data-sections=false
option in llc.

This is because having data sections off when using the
aix-small-local-exec-tls feature is not ideal for performance. As the
small-local-exec-tls region is a limited resource, this space should not
used for variables that may be replaced.

Note, that on AIX, data sections is turned on by default, so this patch
makes it so that a diagnostic is emitted when users explicitly turn off
data sections while using the aix-small-local-exec-tls feature.

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[AIX][TLS] Add target attribute for -maix-small-local-exec-tls option.

This patch adds a target attribute for an AIX-specific option that
informs the compiler that it can use a faster access sequenc

[AIX][TLS] Add target attribute for -maix-small-local-exec-tls option.

This patch adds a target attribute for an AIX-specific option that
informs the compiler that it can use a faster access sequence for the
local-exec TLS model (formally named aix-small-local-exec-tls).

The Clang portion of this option is in D155544.
The initial implementation to generate the faster access sequence is in
D155600.

Differential Revision: https://reviews.llvm.org/D156203

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[PowerPC] Use member function to determine PowerPC Secure PLT

Add a member function isPPC32SecurePlt() to determine whether Secure
PLT is used by the target 32-bit PowerPC operating environment.

Re

[PowerPC] Use member function to determine PowerPC Secure PLT

Add a member function isPPC32SecurePlt() to determine whether Secure
PLT is used by the target 32-bit PowerPC operating environment.

Reviewed By: dim, maskray

Differential Revision: https://reviews.llvm.org/D144444

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[PPC] Add support for tune-cpu attribute

clang (like gcc) has the -mtune= command line option. This option
adds the "tune-cpu" attribute to a function. The intended functionality
is that the schedul

[PPC] Add support for tune-cpu attribute

clang (like gcc) has the -mtune= command line option. This option
adds the "tune-cpu" attribute to a function. The intended functionality
is that the scheduling model of that cpu is used. E.g. -mtune=pwr9 -march=pwr8
generates only instructions supported on pwr8 but uses the scheduling model
of pwr9 for it.
This PR adds the infrastructure to support this in LLVM.
clang support was added in https://reviews.llvm.org/D130526.

Reviewed By: amyk, qiucf

Differential Revision: https://reviews.llvm.org/D138317

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[PowerPC] Enable track-subreg-liveness by default

This option helps some MMA related cases to reduce unnecessary copies.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D108902

[PowerPC] Simplify PPCSubtarget

The flags, initialization of the flags, and the getter methods for
features defined in PPC.td can be generated by TableGen.

Reviewed By: shchenz

Differential Revisi

[PowerPC] Simplify PPCSubtarget

The flags, initialization of the flags, and the getter methods for
features defined in PPC.td can be generated by TableGen.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D140028

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[PowerPC] add a new subtarget feature fastMFLR

Some PowerPC CPU may have slow MFLR instruction, so we need to
schedule the MFLR and its store in function prologue away to
hidden the long latency for

[PowerPC] add a new subtarget feature fastMFLR

Some PowerPC CPU may have slow MFLR instruction, so we need to
schedule the MFLR and its store in function prologue away to
hidden the long latency for slow MFLR instruction.

This patch adds a new feature fastMFLR and the new feature will
be used in https://reviews.llvm.org/D137423.

Reviewed By: RolandF

Differential Revision: https://reviews.llvm.org/D137612

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[PowerPC][Future] Add an ISA Future to go with mcpu=future.

On Power PC we have ISA3.0 for Power 9, ISA3.1 for Power 10.
This patchs adds an ISA for mcpu=future. The idea is to have a placeholder IS

[PowerPC][Future] Add an ISA Future to go with mcpu=future.

On Power PC we have ISA3.0 for Power 9, ISA3.1 for Power 10.
This patchs adds an ISA for mcpu=future. The idea is to have a placeholder ISA
for work that is experimental and may not be supported by existing ISAs.

Reviewed By: lei

Differential Revision: https://reviews.llvm.org/D126075

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Cleanup includes: DebugInfo & CodeGen

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332

[PowerPC] Implement general back2back fusion

Implement 'back-to-back' FX fusion according to Power10 User Manual
'19.1.5.4 Fusion', not enabled by default.

Reviewed By: nemanjai

Differential Revis

[PowerPC] Implement general back2back fusion

Implement 'back-to-back' FX fusion according to Power10 User Manual
'19.1.5.4 Fusion', not enabled by default.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D114345

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[PowerPC] Implement more fusion types for Power10

This implements the rest of Power10 instruction fusion pairs, according
to user manual, including 'wide immediate', 'load compare', 'zero move'
and

[PowerPC] Implement more fusion types for Power10

This implements the rest of Power10 instruction fusion pairs, according
to user manual, including 'wide immediate', 'load compare', 'zero move'
and 'SHA3 assist'.

Only 'SHA3 assist' is enabled by default.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D112912

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[PowerPC] Implement basic macro fusion in Power10

Including basic fusion types around arithmetic and logical instructions.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D111693

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

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