[PowerPC] Fix saving of Link Register when using ROP Protect (#123101)

An optimization was added that tries to move the uses of the mflr
instruction away from the instruction itself. However, this

[PowerPC] Fix saving of Link Register when using ROP Protect (#123101)

An optimization was added that tries to move the uses of the mflr
instruction away from the instruction itself. However, this doesn't work
when we are using the hashst instruction because that instruction needs
to be run before the stack frame is obtained.

This patch disables moving instructions away from the mflr in the case
where ROP protection is being used.

---------

Co-authored-by: Lei Huang <lei@ca.ibm.com>

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[llvm] Mark scavenging spill-slots as *spilled* stack objects. (#122673)

This seems like an oversight when copying code from other backends.

[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)

This patch utilizes getReservedRegs() to find asm clobberable registers.
And to make the result of getReservedRegs() a

[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)

This patch utilizes getReservedRegs() to find asm clobberable registers.
And to make the result of getReservedRegs() accurate, this patch
implements the todo, which is to make r2 allocatable on AIX for some
leaf functions.

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[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that

[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.

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[PowerPC] Use DenseMap::operator[] (NFC) (#107044)

[PPC][AIX] Save/restore r31 when using base pointer (#100182)

When the base pointer r30 is used to hold the stack pointer, r30 is
spilled in the prologue. On AIX registers are saved from highest to

[PPC][AIX] Save/restore r31 when using base pointer (#100182)

When the base pointer r30 is used to hold the stack pointer, r30 is
spilled in the prologue. On AIX registers are saved from highest to
lowest, so r31 also needs to be saved.

Fixes https://github.com/llvm/llvm-project/issues/96411

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CodeGen: Avoid some references to MachineFunction's getMMI (#99652)

MachineFunction's probably should not include a backreference to
the owning MachineModuleInfo. Most of these references were used

CodeGen: Avoid some references to MachineFunction's getMMI (#99652)

MachineFunction's probably should not include a backreference to
the owning MachineModuleInfo. Most of these references were used
just to query the MCContext, which MachineFunction already directly
stores. Other contexts are using it to query the LLVMContext, which
can already be accessed through the IR function reference.

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[PowerPC] use r1 as the frame pointer when there is dynamic alloca

On PPC, when there is dynamic alloca, only r1 points to the backchain.

[PowerPC] return correct frame address for frameaddress intrinsic

[PowerPC] Spill non-volatile registers required for traceback table (#71115)

On AIX we need to spill all [rfv]N-[rfv]31 when a function clobbers
[rfv]N so that the traceback table contains accurate

[PowerPC] Spill non-volatile registers required for traceback table (#71115)

On AIX we need to spill all [rfv]N-[rfv]31 when a function clobbers
[rfv]N so that the traceback table contains accurate information.

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[NFC] Refactor looping over recomputeLiveIns into function (#88040)

https://github.com/llvm/llvm-project/pull/79940 put calls to
recomputeLiveIns into
a loop, to repeatedly call the function until

[NFC] Refactor looping over recomputeLiveIns into function (#88040)

https://github.com/llvm/llvm-project/pull/79940 put calls to
recomputeLiveIns into
a loop, to repeatedly call the function until the computation converges.
However,
this repeats a lot of code. This changes moves the loop into a function
to simplify
the handling.

Note that this changes the order in which recomputeLiveIns is called.
For example,

```
bool anyChange = false;
do {
anyChange = recomputeLiveIns(*ExitMBB) || recomputeLiveIns(*LoopMBB);
} while (anyChange);
```

only begins to recompute the live-ins for LoopMBB after the computation
for ExitMBB
has converged. With this change, all basic blocks have a recomputation
of the live-ins
for each loop iteration. This can result in less or more calls,
depending on the
situation.

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[PowerPC] Clang format (NFC).

[PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098)

Delete the code that skips the CFI for the condition register on ELF32.
The code checked !MustSaveCR, which happened only when
Subt

[PowerPC] provide CFI for ELF32 to unwind cr2, cr3, cr4 (#83098)

Delete the code that skips the CFI for the condition register on ELF32.
The code checked !MustSaveCR, which happened only when
Subtarget.is32BitELFABI(), where spillCalleeSavedRegisters is spilling
cr in a different way. The spill was missing CFI. After deleting this
code, a spill of cr2 to cr4 gets CFI in the same way as a spill of r14
to r31.

Fixes #83094

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Refactor recomputeLiveIns to converge on added MachineBasicBlocks (#79940)

This is a fix for the regression seen in
https://github.com/llvm/llvm-project/pull/79498

> Currently, the way that reco

Refactor recomputeLiveIns to converge on added MachineBasicBlocks (#79940)

This is a fix for the regression seen in
https://github.com/llvm/llvm-project/pull/79498

> Currently, the way that recomputeLiveIns works is that it will
recompute the livein registers for that MachineBasicBlock but it matters
what order you call recomputeLiveIn which can result in incorrect
register allocations down the line.

Now we do not recompute the entire CFG but we do ensure that the newly
added MBB do reach convergence.

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Revert "Refactor recomputeLiveIns to operate on whole CFG (#79498)"

This reverts commit 59bf60519fc30d9d36c86abd83093b068f6b1e4b.

Introduces a major compile-time regression.

Refactor recomputeLiveIns to operate on whole CFG (#79498)

Currently, the way that recomputeLiveIns works is that it will recompute
the livein registers for that MachineBasicBlock but it matters wh

Refactor recomputeLiveIns to operate on whole CFG (#79498)

Currently, the way that recomputeLiveIns works is that it will recompute
the livein registers for that MachineBasicBlock but it matters what
order you call recomputeLiveIn which can result in incorrect register
allocations down the line.

This PR fixes that by simply recomputing the liveins for the entire CFG
until convergence is achieved. This makes it harder to introduce subtle
bugs which alter liveness.

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[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled (#73940)

This was modifying a container as it iterated it, which tripped a check
in libstdc++'s debug checks

[llvm][PowerPC] Correct handling of spill slots for SPE when EXPENSIVE_CHECKS is enabled (#73940)

This was modifying a container as it iterated it, which tripped a check
in libstdc++'s debug checks.

Instead, just assign to the item via the reference we already have.

This fixes the following expensive checks failures on my machine:
LLVM :: CodeGen/PowerPC/fp-strict.ll
LLVM :: CodeGen/PowerPC/pr55463.ll
LLVM :: CodeGen/PowerPC/register-pressure.ll
LLVM :: CodeGen/PowerPC/spe.ll

Which are some of the tests noted by #68594.

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[RegScavenger] Simplify state tracking for backwards scavenging (#71202)

Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the sta

[RegScavenger] Simplify state tracking for backwards scavenging (#71202)

Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the start or end of a
basic block without a separate (and poorly named) Tracking flag.

This changes the API of the backward(MachineBasicBlock::iterator I)
method, which now recedes to the state just before, instead of just
after, *I. Some clients are simplified by this change.

There is one small functional change shown in the lit tests where
multiple spilled registers all need to be reloaded before the same
instruction. The reloads will now be inserted in the opposite order.
This should not affect correctness.

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[PEI][PowerPC] Fix false alarm of stack size limit (#65559)

PPC64 allows stack size up to ((2^63)-1) bytes. Currently llc reports
```
warning: stack frame size (4294967568) exceeds limit (42949672

[PEI][PowerPC] Fix false alarm of stack size limit (#65559)

PPC64 allows stack size up to ((2^63)-1) bytes. Currently llc reports
```
warning: stack frame size (4294967568) exceeds limit (4294967295) in function 'main'
```
if the stack allocated is larger than 4G.

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[PowerPC/SPE] powerpcspe load and store instruction has
8-bit offset instead of 16-bit unlike other load/store instructions.
so if stack grows any further than 8-bit, create one emergency slot
for sp

[PowerPC/SPE] powerpcspe load and store instruction has
8-bit offset instead of 16-bit unlike other load/store instructions.
so if stack grows any further than 8-bit, create one emergency slot
for spilling.

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PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs

The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
An

PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs

The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
And emit store /reload instructions for the required halves.

PR : https://github.com/llvm/llvm-project/issues/57307

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D152437

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[PowerPC] Avoid RegScavenger::forward in PPCFrameLowering

RegScavenger::backward is preferred because it does not rely on accurate
kill flags.

Differential Revision: https://reviews.llvm.org/D150558

[Target] Use range-based for loops (NFC)

[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot

With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful wit

[CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot

With D134950, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D138656

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[PowerPC] store the LR before stack update for big offsets.

For case that LROffset + FrameSize can not be encoded to the LR
store instruction, we have to store the LR before the stack update.