[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

Use llvm::endianness::{big,little,native} (NFC)

Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces suppo

Use llvm::endianness::{big,little,native} (NFC)

Note that llvm::support::endianness has been renamed to
llvm::endianness while becoming an enum class as opposed to an
enum. This patch replaces support::{big,little,native} with
llvm::endianness::{big,little,native}.

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Use llvm::endianness (NFC)

Now that llvm::support::endianness has been renamed to
llvm::endianness, we can use the shorter form. This patch replaces
support::endianness with llvm::endianness.

[PPC] Fix layering issues between MCTargetDesc and CodeGen

See issue #64166 for more information about the layering issue.

The PPCMCTargetDesc library was including CodeGen headers such as
PPCInstr

[PPC] Fix layering issues between MCTargetDesc and CodeGen

See issue #64166 for more information about the layering issue.

The PPCMCTargetDesc library was including CodeGen headers such as
PPCInstrInfo.h and calling inline functions in them. This doesn't work
in the Bazel build, and is error-prone. If the inline function moves to
a cpp file, it will result in linker errors.

To address the issue, I moved several inline functions to
PPCMCTargetDesc.cpp, and declared them in the PPC namespace in
PPCMCTargetDesc.h, which seemed like the most straightforward fix.

Differential Revision: https://reviews.llvm.org/D156488

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[AArch64,AVR,PowerPC] Migrate to new encodeInstruction that uses SmallVectorImpl<char>. NFC

Similar to 49488490d195591bfc90daef111cd7293f8c80aa.

[NFC][TargetParser] Remove llvm/ADT/Triple.h

I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.

[PowerPC] Switch to by-name matching for instructions (part 2 of 2).

This is a follow-on to https://reviews.llvm.org/D134073.

Currently, all of the "memri"-style complex operands, which contain
bot

[PowerPC] Switch to by-name matching for instructions (part 2 of 2).

This is a follow-on to https://reviews.llvm.org/D134073.

Currently, all of the "memri"-style complex operands, which contain
both a register and an immediate, are encoded into a single field in
the instruction definition. This requires complex encoders/decoders,
and instruction definitions that insert and extract the correct parts
of the bits.

Now, switch to naming and encoding/decoding the sub-operands
separately.

Thus, we can now disable useDeprecatedPositionallyEncodedOperands.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D137670

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[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added

[CodeGen] Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Recommitted with some fixes for the leftover MCII variables in release
builds.

Differential Revision: https://reviews.llvm.org/D129506

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Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are givin

Revert "Move instruction predicate verification to emitInstruction"

This reverts commit e2fb8c0f4b940e0285ee36c112469fa75d4b60ff as it does
not build for Release builds, and some buildbots are giving more warning
than I saw locally. Reverting to fix those issues.

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Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Targ

Move instruction predicate verification to emitInstruction

D25618 added a method to verify the instruction predicates for an
emitted instruction, through verifyInstructionPredicates added into
<Target>MCCodeEmitter::encodeInstruction. This is a very useful idea,
but the implementation inside MCCodeEmitter made it only fire for object
files, not assembly which most of the llvm test suite uses.

This patch moves the code into the <Target>_MC::verifyInstructionPredicates
method, inside the InstrInfo. The allows it to be called from other
places, such as in this patch where it is called from the
<Target>AsmPrinter::emitInstruction methods which should trigger for
both assembly and object files. It can also be called from other places
such as verifyInstruction, but that is not done here (it tends to catch
errors earlier, but in reality just shows all the mir tests that have
incorrect feature predicates). The interface was also simplified
slightly, moving computeAvailableFeatures into the function so that it
does not need to be called externally.

The ARM, AMDGPU (but not R600), AVR, Mips and X86 backends all currently
show errors in the test-suite, so have been disabled with FIXME
comments.

Differential Revision: https://reviews.llvm.org/D129506

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[PowerPC][NFC] Add a function to determine if a call needs to be NOTOC.

Add the isNoTOCCallInstr function to PPCInstrInfo to determine if a call opcode
does not need a TOC restore after the call. Al

[PowerPC][NFC] Add a function to determine if a call needs to be NOTOC.

Add the isNoTOCCallInstr function to PPCInstrInfo to determine if a call opcode
does not need a TOC restore after the call. All call opcodes should be listed in
this function. A default unreachable in this function should force future call
opcodes to also be added.

This is a follow up patch to D122012

Reviewed By: jsji, shchenz

Differential Revision: https://reviews.llvm.org/D124415

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[PowerPC] The BL8_NOTOC_RM instruction needs to produce a notoc relocation.

The BL8_NOTOC_RM instruction was incorrectly producing a relocation that reqired
a TOC restore after the call. This patch

[PowerPC] The BL8_NOTOC_RM instruction needs to produce a notoc relocation.

The BL8_NOTOC_RM instruction was incorrectly producing a relocation that reqired
a TOC restore after the call. This patch fixes that issue and the notoc
relocation is now used.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D122012

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[PowerPC] Allow absolute expressions in relocations

The Linux kernel build uses absolute expressions suffixed with @lo/@ha
relocations. This currently doesn't work for DS/DQ form instructions and
th

[PowerPC] Allow absolute expressions in relocations

The Linux kernel build uses absolute expressions suffixed with @lo/@ha
relocations. This currently doesn't work for DS/DQ form instructions and
there is no reason for it not to. It also works with GAS.
This patch allows this as long as the value is a multiple of 4/16
for DS/DQ form.

Differential revision: https://reviews.llvm.org/D115419

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[NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter`

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D119846

[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will b

[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will be used for ROP Protection.
This patch adds the four instructions.

Reviewed By: nemanjai, amyk, #powerpc

Differential Revision: https://reviews.llvm.org/D99375

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Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"

This reverts commit 16fe741c69429235210c03c46420f8fa6aece4a1.

Reason: Broke the UBSan buildbots. More information available in the
pha

Revert "[PowerPC] Add ROP Protection Instructions for PowerPC"

This reverts commit 16fe741c69429235210c03c46420f8fa6aece4a1.

Reason: Broke the UBSan buildbots. More information available in the
phabricator review: https://reviews.llvm.org/D99375

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[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will b

[PowerPC] Add ROP Protection Instructions for PowerPC

There are four new PowerPC instructions that are introduced in
Power 10. They are hashst, hashchk, hashstp, hashchkp.

These instructions will be used for ROP Protection.
This patch adds the four instructions.

Reviewed By: nemanjai, amyk, #powerpc

Differential Revision: https://reviews.llvm.org/D99375

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[PowerPC] Add outer product instructions for MMA

This patch adds outer product instructions for MMA, including related infrastructure, and their tests.

Depends on D84968.

Reviewed By: #powerpc, bs

[PowerPC] Add outer product instructions for MMA

This patch adds outer product instructions for MMA, including related infrastructure, and their tests.

Depends on D84968.

Reviewed By: #powerpc, bsaleil, amyk

Differential Revision: https://reviews.llvm.org/D88043

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[PowerPC][PCRelative] Thread Local Storage Support for Local Dynamic

This patch is the initial support for the Local Dynamic Thread Local Storage
model to produce code sequence and relocation correc

[PowerPC][PCRelative] Thread Local Storage Support for Local Dynamic

This patch is the initial support for the Local Dynamic Thread Local Storage
model to produce code sequence and relocation correct to the ABI for the model
when using PC relative memory operations.

Differential Revision: https://reviews.llvm.org/D87721

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[PowerPC][PCRelative] Thread Local Storage Support for Initial Exec

This patch is the initial support for the Intial Exec Thread Local
Local Storage model to produce code sequence and relocations co

[PowerPC][PCRelative] Thread Local Storage Support for Initial Exec

This patch is the initial support for the Intial Exec Thread Local
Local Storage model to produce code sequence and relocations correct
to the ABI for the model when using PC relative memory operations.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D81947

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[PowerPC][PCRelative] Thread Local Storage Support for General Dynamic

This patch is the initial support for the General Dynamic Thread Local
Local Storage model to produce code sequence and relocat

[PowerPC][PCRelative] Thread Local Storage Support for General Dynamic

This patch is the initial support for the General Dynamic Thread Local
Local Storage model to produce code sequence and relocations correct
to the ABI for the model when using PC relative memory operations.

Patch by: NeHuang

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D82315

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[PowerPC] Split s34imm into two types

Currently the instruction paddi always takes s34imm as the type for the
34 bit immediate. However, the PC Relative form of the instruction should
not produce th

[PowerPC] Split s34imm into two types

Currently the instruction paddi always takes s34imm as the type for the
34 bit immediate. However, the PC Relative form of the instruction should
not produce the same fixup as the non PC Relative form.
This patch splits the s34imm type into s34imm and s34imm_pcrel so that two
different fixups can be emitted.

Reviewed By: nemanjai, #powerpc, kamaub

Differential Revision: https://reviews.llvm.org/D83255

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Temporarily Revert "[PowerPC] Split s34imm into two types"
as it was failing in Release+Asserts mode with an assert.

This reverts commit bd2068031121adf5a0e28d9306a1741d6f0bbd87.

[PowerPC] Split s34imm into two types

Currently the instruction paddi always takes s34imm as the type for the
34 bit immediate. However, the PC Relative form of the instruction should
not produce th

[PowerPC] Split s34imm into two types

Currently the instruction paddi always takes s34imm as the type for the
34 bit immediate. However, the PC Relative form of the instruction should
not produce the same fixup as the non PC Relative form.
This patch splits the s34imm type into s34imm and s34imm_pcrel so that two
different fixups can be emitted.

Reviewed By: kamaub, nemanjai

Differential Revision: https://reviews.llvm.org/D83255

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[Target/PPC] Fold inside an assertion.

Pointed out by dblaikie.