[M68k] implement move to and from sr (#111145)

This PR enables the use of the status register in inline assembly.
This is necessary to, for example, set and retrieve the current
interrupt mask.

[M68k] implement move to and from sr (#111145)

This PR enables the use of the status register in inline assembly.
This is necessary to, for example, set and retrieve the current
interrupt mask.

---------

Co-authored-by: kirk <knickish@gmail.com>

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[M68k] Add remaining addressing modes for Atomic operations (#115523)

Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`,

[M68k] Add remaining addressing modes for Atomic operations (#115523)

Had been doing this piece by piece, but makes more sense to do it in a
single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD`
addressing modes for atomic operations, along with a variety of tests.

The `CodeModel` tests have been rearranged, as some of the new
addressing modes are only exercised under some combinations of
`CodeModel` and relocation mode

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[M68k][MC] Add fmove.l from / to fp control registers

Including splitting up the FPCR register class into classes with finer
granularities.
Right now we only support address / data registers as sour

[M68k][MC] Add fmove.l from / to fp control registers

Including splitting up the FPCR register class into classes with finer
granularities.
Right now we only support address / data registers as source /
destinations.

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[M68k] Basic FP register files and FMOVE implementations

- FP registers and register classes definitions
- MC support for FP registers
- MC support for the FPDR -> FPDR variant of FMOVE/FSMOVE

[M68k] Basic FP register files and FMOVE implementations

- FP registers and register classes definitions
- MC support for FP registers
- MC support for the FPDR -> FPDR variant of FMOVE/FSMOVE/FDSMOVE

Note that we don't implement 32/64-bit FP registers with subregisters since
f32/f64 values will be converted to f80 upon storing into a register,
rather than occupying part of the register.
So we only use register classes with different value types to distinguish
them.

Differential Revision: https://reviews.llvm.org/D147480

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[M68k][Disassembler] Use custom decoder for 32-bit immediates

32-bit immediates require special cares because they go across the
normal word (16 bits) boundaries.
This patch also fixes some incorrec

[M68k][Disassembler] Use custom decoder for 32-bit immediates

32-bit immediates require special cares because they go across the
normal word (16 bits) boundaries.
This patch also fixes some incorrect disassembler test cases.

Differential Revision: https://reviews.llvm.org/D142080

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[M68k][Disassembler] Cleanup unused variables. NFC

- Remove `MaxInstrWord` in M68kDisassembler.cpp.
- Remove `MCII` field in `M68kDisassembler` class.

NFC.

[M68k] Fix a bug in disassembler

Sorry for my reckless patch. In some cases `RoundUp` is less than
the bit width of APInt. We need to check this before we do zext.

[NFC][M68k] Replace `APInt::zextOrSelf` with `APInt::zext`

This is a follow up to D125558

[M68k][Disassembler] Fix decoding conflict

This diff fixes decoding conflict between these pair of instructions:

ADD(16|32)dd / ADD(16|32)dr
SUB(16|32)dd / SUB(16|32)dr
AND(16|32)dd / AND(16|32)dr

[M68k][Disassembler] Fix decoding conflict

This diff fixes decoding conflict between these pair of instructions:

ADD(16|32)dd / ADD(16|32)dr
SUB(16|32)dd / SUB(16|32)dr
AND(16|32)dd / AND(16|32)dr
OR(16|32)dd / OR(16|32)dr

Reviewed By: ricky26

Differential Revision: https://reviews.llvm.org/D125861

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[M68k][Disassembler] Adopt the new variable length decoder

This is an example usage of D120958.

After these patches are landed, we can strip off the codebeads officially.

Reviewed By: myhsu

Diffe

[M68k][Disassembler] Adopt the new variable length decoder

This is an example usage of D120958.

After these patches are landed, we can strip off the codebeads officially.

Reviewed By: myhsu

Differential Revision: https://reviews.llvm.org/D120960

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[M68k][NFC] Fix file header

Let all file header have the same style. NFC.

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

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[M68k] Avoid UB in disassembler

When reading 32 bits a 32-bit shift would be executed.

This is undefined behaviour, but in this case we can just replace the
entire scratch value to avoid it.

Diffe

[M68k] Avoid UB in disassembler

When reading 32 bits a 32-bit shift would be executed.

This is undefined behaviour, but in this case we can just replace the
entire scratch value to avoid it.

Differential Revision: https://reviews.llvm.org/D110769

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[M68k][Disassembler][NFC] Decorate dump methods with LLVM_DUMP_METHOD

And guard them with proper macro conditions. NFC.

[M68k] Implement Disassembler

This is an implementation of a disassembler for M68k.

Differential Revision: https://reviews.llvm.org/D98540