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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4 |
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| #
77523f9d |
| 02-Sep-2024 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Remove unnecessary increment operations
`HighMask` is the value that sets bits from `Msb+1` to 63 to 1, while
the other bits are set to 0.
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| #
18e35d8f |
| 31-Aug-2024 |
Vitaly Buka <vitalybuka@google.com> |
[LoongArch] Don't left shift negative value (#106812)
Fixed another UB from #106332.
Detected here https://lab.llvm.org/buildbot/#/builders/169/builds/2662
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| #
432e9f44 |
| 30-Aug-2024 |
Vitaly Buka <vitalybuka@google.com> |
[llvm][LoongArch] Avoid shift overflow (#106785)
Follow up fix to #106332
`LoongArchMatInt.cpp:96:33: runtime error: shift exponent 64 is too
large for 64-bit type`
https://lab.llvm.org/buildbo
[llvm][LoongArch] Avoid shift overflow (#106785)
Follow up fix to #106332
`LoongArchMatInt.cpp:96:33: runtime error: shift exponent 64 is too
large for 64-bit type`
https://lab.llvm.org/buildbot/#/builders/169/builds/2681
show more ...
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| #
c55e24b8 |
| 30-Aug-2024 |
David Spickett <david.spickett@linaro.org> |
[llvm][LoongArch] Fix BSTRINS_D test failures on 32 bit hosts
eaf87d32754beb5bec10bab517bf56e25575b48e added new code that uses
64 bit types and ULL for constants, mostly, but a few UL snuck in.
UL
[llvm][LoongArch] Fix BSTRINS_D test failures on 32 bit hosts
eaf87d32754beb5bec10bab517bf56e25575b48e added new code that uses
64 bit types and ULL for constants, mostly, but a few UL snuck in.
UL is still 4 bytes on 32 bit, ULL is 8.
This fixes test failures on 32 bit Arm:
https://lab.llvm.org/buildbot/#/builders/39/builds/1338
show more ...
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| #
eaf87d32 |
| 27-Aug-2024 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Optimize for immediate value materialization using BSTRINS_D instruction
Reviewed By: heiher, SixWeining
Pull Request: https://github.com/llvm/llvm-project/pull/106332
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Revision tags: llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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| #
407b613d |
| 15-Apr-2022 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Add support for selecting constant materializations.
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and
ADDI_W instructions.
According to the sign-extended behavior o
[LoongArch] Add support for selecting constant materializations.
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and
ADDI_W instructions.
According to the sign-extended behavior of these instructions
(except ORI), the generated instruction sequence can be improved.
For example, load -1 into general register:
The ADDI_W instruction performs the operation that the [31:0] bit data
in the general register `rj` plus the 12-bit immediate `simm12` sign
extension 32-bit data; the resultant [31:0] bit is sign extension, then
written into the general register `rd`.
Normal sequence:
```
lu12i.w $a0, -1
ori $a0, $a0, 2048
```
Improved with sign-extended instruction:
```
addi.w $a0, $zero, -1
```
Reviewed By: SixWeining, MaskRay
Differential Revision: https://reviews.llvm.org/D123290
show more ...
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