[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that

[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::hasFP()` (#106014)

Some targets (e.g. PPC and Hexagon) already did this. I think it's best
to do this consistently so that frontend authors don't run into
inconsistent results when they emit `naked` functions. For example, in
Zig, we had to change our emit code to also set `frame-pointer=none` to
get reliable results across targets.

Note: I don't have commit access.

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[LoongArch] Revert `sp` adjustment in prologue (#88110)

After commit 18c5f3c3 ("[RegisterScavenger][RISCV] Don't search for
FrameSetup instrs if we were searching from Non-FrameSetup instrs"), we

[LoongArch] Revert `sp` adjustment in prologue (#88110)

After commit 18c5f3c3 ("[RegisterScavenger][RISCV] Don't search for
FrameSetup instrs if we were searching from Non-FrameSetup instrs"), we
can revert the `sp` adjustment 4e2364a2 ("[LoongArch] Add emergency
spill slot for GPR for large frames") to generate better code, as the
issue with `RegScavenger` has been resolved.

Fixes #88109

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[LoongArch] Enable shrink wrapping when optimize the function

We set it conservatively so that it is turned on when optimization
is enabled, i.e. when the optimization level is not `O0`.

Reviewed B

[LoongArch] Enable shrink wrapping when optimize the function

We set it conservatively so that it is turned on when optimization
is enabled, i.e. when the optimization level is not `O0`.

Reviewed By: xen0n

Differential Revision: https://reviews.llvm.org/D142876

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[LoongArch] Override TargetFrameLowering::spillCalleeSavedRegisters

When using `llvm.returnaddress` intrinsic, special handling is required
for the spill of the `RA` register. Otherwise it will caus

[LoongArch] Override TargetFrameLowering::spillCalleeSavedRegisters

When using `llvm.returnaddress` intrinsic, special handling is required
for the spill of the `RA` register. Otherwise it will cause the verifier
fail in some cases (e.g. pr17377.c of the GCC C Torture Suite).

Specifically:
```
*** Bad machine code: Using an undefined physical register ***
- function: f
- basic block: %bb.0 entry (0xd94d18)
- instruction: ST_D killed $r1, $r22, -40 :: (store (s64) into %stack.2)
- operand 0: killed $r1
```

Reviewed By: SixWeining

Differential Revision: https://reviews.llvm.org/D137387

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[LoongArch] Add emergency spill slot for GPR for large frames

An emergency spill slot is created when the stack size cannot be
represented by an 11-bit signed number.

This patch also modifies how t

[LoongArch] Add emergency spill slot for GPR for large frames

An emergency spill slot is created when the stack size cannot be
represented by an 11-bit signed number.

This patch also modifies how the `sp` is adjusted in the prologue.

`RegScavenger` will place the spill instruction before the prologue
if a VReg is created in the prologue. This will pollute the caller's
stack data. Therefore, until there is better way, we just use the
`addi.w/d` instruction for stack adjustment to ensure that VReg will
not be created. (RISCV has the same issue #58286)

Due to the addition of emergency spill slot, some test cases that use
exact stacksize need to be updated.

Differential Revision: https://reviews.llvm.org/D135757

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[LoongArch] Split SP adjustment

This patch split the SP adjustment to reduce the instructions in
prologue and epilogue. In this way, the offset of the callee saved
register could fit in a single sto

[LoongArch] Split SP adjustment

This patch split the SP adjustment to reduce the instructions in
prologue and epilogue. In this way, the offset of the callee saved
register could fit in a single store.

Similar to D68011(RISCV).

Differential Revision: https://reviews.llvm.org/D136222

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[LoongArch] Support for varargs

This patch ensures the `$fp` always points to the bottom of the vararg
spill region.
Includes support for expand `ISD::DYNAMIC_STACKALLOC`.

Differential Revision: ht

[LoongArch] Support for varargs

This patch ensures the `$fp` always points to the bottom of the vararg
spill region.
Includes support for expand `ISD::DYNAMIC_STACKALLOC`.

Differential Revision: https://reviews.llvm.org/D130250

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[LoongArch] Use `end namespace xxx` style comment. NFC

[LoongArch] Implement prologue/epilogue insertion

Differential Revision: https://reviews.llvm.org/D128432

[LoongArch] Support lowering FrameIndex

Ensure callee-saved registers are accessed relative to the stackpointer.

Differential Revision: https://reviews.llvm.org/D128430

[LoongArch] Add initial support for function calls

Note that this is just enough for simple function call examples to
generate working code.

A good portion of this patch is the extra functions that

[LoongArch] Add initial support for function calls

Note that this is just enough for simple function call examples to
generate working code.

A good portion of this patch is the extra functions that needed to be
implemented to support the test case. e.g. storeRegToStackSlot,
loadRegFromStackSlot, eliminateFrameIndex.

Differential Revision: https://reviews.llvm.org/D128429

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[LoongArch 4/6] Add basic tablegen infra for LoongArch

This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.

For now, only add instructi

[LoongArch 4/6] Add basic tablegen infra for LoongArch

This patch introduces basic tablegen infra such as
LoongArch{InstrFormats,InstrInfo,RegisterInfo,CallingConv,}.td.

For now, only add instruction definitions for LoongArch basic integer
operations.
Our initial target is a working MC layer rather than codegen,
so appropriate SelectionDAG patterns will come later.

Differential revision: https://reviews.llvm.org/D115861

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