[Hexagon] Add missing pattern for v8i1 type (#120703)

HexagonISD::PFALSE and PTRUE patterns do not form independently in
general as they are treated like operands of all 0s or all 1s. Eg: i32 =
tr

[Hexagon] Add missing pattern for v8i1 type (#120703)

HexagonISD::PFALSE and PTRUE patterns do not form independently in
general as they are treated like operands of all 0s or all 1s. Eg: i32 =
transfer HEXAGONISD::PFALSE.
In this case, v8i1 = HEXAGONISD::PFALSE is formed independently without
accompanying opcode.

This patch adds a pattern to transfer all 0s or all 1s to a scalar
register and then use that register and this PFALSE/PTRUE opcode to
transfer to a predicate register like v8i1.

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[hexagon] Add support for llvm.debugtrap (#117049)

Also: set `hasSideEffects` on `Y2_break` instruction.

[Hexagon] Use getSignedConstant for RoundTo8 XForm

To handle negative offset addrmodes correctly.

Fixes https://github.com/llvm/llvm-project/pull/117558#issuecomment-2510208764.

[Hexagon] Avoid implicit truncation in getConstant()

Use getSignedConstant() or change variable type as appropriate.
This will avoid assertion failures when implicit truncation is
disabled.

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 8988148003

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

As far as I can tell, this pull request was not approved, and
did not go through an RFC on discourse.

This reverts commit 89881480030f48f83af668175b70a9798edca2fb.
This reverts commit 225d8fc8eb24fb797154c1ef6dcbe5ba033142da.

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Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AAr

Intrinsic: introduce minimumnum and maximumnum (#93841)

Currently, on different platform, the behaivor of llvm.minnum is
different if one operand is sNaN:

When we compare sNaN vs NUM:

ARM/AArch64/PowerPC: follow the IEEE754-2008's minNUM: return qNaN.
RISC-V/Hexagon follow the IEEE754-2019's minimumNumber: return NUM. X86:
Returns NUM but not same with IEEE754-2019's minimumNumber as
+0.0 is not always greater than -0.0.
MIPS/LoongArch/Generic: return NUM.
LIBCALL: returns qNaN.

So, let's introduce llvm.minmumnum/llvm.maximumnum, which always follow
IEEE754-2019's minimumNumber/maximumNumber.

Half-fix: #93033

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[Hexagon] Implement @llvm.readsteadycounter() (#93247)

This commit was inspired by @kparzysz's ab57c2bad3dc ([Hexagon]
Implement @llvm.readcyclecounter(), 2017-02-22)

[Hexagon] Fix zero extension of bit predicates with vtrunehb (#81772)

vector extension from v4i1 to v4i8 generates an incorrect word. This
patch uses a vtrunehb for truncation to fix the bug.

SelectionDAG: Swap operands of atomic_store

Irritatingly, atomic_store had operands in the opposite order from
regular store. This made it difficult to share patterns between
regular and atomic stor

SelectionDAG: Swap operands of atomic_store

Irritatingly, atomic_store had operands in the opposite order from
regular store. This made it difficult to share patterns between
regular and atomic stores.

There was a previous incomplete attempt to move atomic_store into the
regular StoreSDNode which would be better.

I think it was a mistake for all atomicrmw to swap the operand order,
so maybe it's better to take this one step further.

https://reviews.llvm.org/D123143

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[Hexagon] Add missing patterns for boolean [v]selects

Fixes https://github.com/llvm/llvm-project/issues/59663

[Hexagon] Handle all compares of i1 and vNi1

Fixes https://github.com/llvm/llvm-project/issues/63363

[Hexagon] Add missing patterns for truncate to vNi1

[Hexagon] Generate correct instruction for store i1, ($Rs<<$u2 + $Rt)

Fixes https://github.com/llvm/llvm-project/issues/63359

[Hexagon] Add patterns for bspap/bitreverse for scalar vectors

Fixes https://github.com/llvm/llvm-project/issues/62474

[Targets] Rename Flag->Glue. NFC

Long long ago Glue was called Flag, and it was never completely
renamed.

[Hexagon] Add missing patterns for select

Fixes https://github.com/llvm/llvm-project/issues/59077.

[Hexagon] Add missing patterns for mulhs/mulhu

[Hexagon] Improve handling of 32-bit mulh/mul_lohi on HVX

Handle MULH[US] by normalizing them into newly invented nodes
HexagonISD::(S|U|US)MUL_LOHI. On HVX v60, if only the high part of
SMUL_LOHI i

[Hexagon] Improve handling of 32-bit mulh/mul_lohi on HVX

Handle MULH[US] by normalizing them into newly invented nodes
HexagonISD::(S|U|US)MUL_LOHI. On HVX v60, if only the high part of
SMUL_LOHI is used, use the original MULHS expansion. In all other
cases, expand the full product.
On HVX v62, always expand the full product.

Introduce Hexagon-specific LLVM IR intrinsics for 32x32 multiplication
returning low/high parts.

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[Hexagon] Lower funnel shifts for HVX

HVX v62+ has bidirectional shifts, which do not mask the shift amount to
the bit width. Instead, the shift amount is sign-extended from the log(BW)
bit value, a

[Hexagon] Lower funnel shifts for HVX

HVX v62+ has bidirectional shifts, which do not mask the shift amount to
the bit width. Instead, the shift amount is sign-extended from the log(BW)
bit value, and a negative value causes a shift in the other direction.
For the shift amount being -log(BW), this reversed shift will shift all
bits out, inserting 0s or sign bits depending on the type and direction.

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[Hexagon] Avoid some unnecessary sign-extend instructions

Simplify (sext_inreg (extractu ...)) -> (extract ...) where appropriate.

[Hexagon] Implement [SU]INT_TO_FP and FP_TO_[SU]INT for HVX

[Hexagon] Create an intrinsic to profile using a custom handler

The intrinsic is lowered into a hexagon pseudo instruction which
after register allocation is expanded into A2_tfrsi and J2_call.

[Hexagon] Handle L2_loadb[sz]w[24]_io in HII::isValidOffset

[Hexagon] Conversions to/from FP types, HVX and scalar

Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
Co-authored-by: Sumanth Gundapaneni <sgundapa@quicinc.com>

[Hexagon] Handle floating point splats

Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>