Reject invalid imod values in t2CPS instructions.

llvm-svn: 138306

Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.

llvm-svn: 138269

Fix another batch of VLD/VST decoding crashes discovered by randomized testing.

llvm-svn: 138255

Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.

llvm-svn: 138251

Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.

llvm-svn: 138246

STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
Found by randomized testing.

llvm-svn: 138003

Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.

llvm-svn: 138000

Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.

llvm-svn: 137997

Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995

Tidy up. 80 columns.

llvm-svn: 137881

ARM clean up the imm_sr operand class representation.

Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely.

ARM clean up the imm_sr operand class representation.

Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879

show more ...

Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.

llvm-svn: 137838

Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by Jame

Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830

show more ...

Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.

llvm-svn: 137787

Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.

llvm-svn: 137686

Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647

Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.

llvm-svn: 137635

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

llvm-svn: 137502

Fix decoding of ARM-mode STRH.

llvm-svn: 137499

Fix decoding of pre-indexed stores.

llvm-svn: 137487

Separate decoding for STREXD and LDREXD to make each work better.

llvm-svn: 137476

ARM STRT assembly parsing and encoding.

llvm-svn: 137372

Add another accidentally omitted predicate operand.

llvm-svn: 137370

Add missing predicate operand on SMLA and friends.

llvm-svn: 137368

Fix decoding support for STREXD and LDREXD.

llvm-svn: 137356