ARM refactor more NEON VLD/VST instructions to use composite physregs

Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150

Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.

llvm-svn: 152127

ARM Refactor VLD/VST spaced pair instructions.

Use the new composite physical registers.

llvm-svn: 152063

ARM refactor away a bunch of VLD/VST pseudo instructions.

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid

ARM refactor away a bunch of VLD/VST pseudo instructions.

With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045

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Make MemoryObject accessor members const again

llvm-svn: 151687

Fix the symbolic operand added for the C disassmbler API for the ARM bl
thumb instruction. The PC adjustment is +4 in Thumb mode and +8 in ARM mode.

llvm-svn: 151530

Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there

Updated the llvm-mc disassembler C API to support for the X86 target.
rdar://10873652

As part of this I updated the llvm-mc disassembler C API to always call the
SymbolLookUp call back even if there is no getOpInfo call back. If there is a
getOpInfo call back that is tried first and then if that gets no information
then the SymbolLookUp is called. I also made the code more robust by
memset(3)'ing to zero the LLVMOpInfo1 struct before then setting
SymbolicOp.Value before for the call to getOpInfo. And also don't use any
values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't
use any of the ReferenceType or ReferenceName values from SymbolLookUp if it
returns NULL. rdar://10873563 and rdar://10873683

For the X86 target also fixed bugs so the annotations get printed.

Also fixed a few places in the ARM target that was not producing symbolic
operands for some instructions. rdar://10878166

llvm-svn: 151267

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

llvm-svn: 150878

Make the EDis tables const.

llvm-svn: 150304

Convert assert(0) to llvm_unreachable

llvm-svn: 149961

Enable streaming of bitcode

This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.

llvm-svn: 149918

More dead code removal (using -Wunreachable-code)

llvm-svn: 148578

ARM NEON VTBL/VTBX assembly parsing and encoding.

llvm-svn: 146691

ARM NEON refactor VST2 w/ writeback instructions.

In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588

ARM NEON VST2 assembly parsing and encoding.

Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need mo

ARM NEON VST2 assembly parsing and encoding.

Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579

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ARM assembly parsing and encoding for VLD2 with writeback.

Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
regi

ARM assembly parsing and encoding for VLD2 with writeback.

Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.

llvm-svn: 146278

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Remove unused variable

llvm-svn: 145517

ARM parsing for VLD1 all lanes, with writeback.

llvm-svn: 145510

ARM assembly parsing and encoding for four-register VST1.

llvm-svn: 145450

ARM assembly parsing and encoding for three-register VST1.

llvm-svn: 145442

Fix a misplaced paren bug.

llvm-svn: 144692

Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.

llvm-svn: 144683

Re-apply 144430, this time with the associated isel and disassmbler bits.

Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437

Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.

llvm-svn: 144384

The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552.

llvm-svn: 143553