[CodeGen] Use MCRegister for ignoreCSRForAllocationOrder. (#123685)

[ARM] Add Cortex-A510 CPU for AArch32 (#118811)

This core was originally AArch64-only, but the r1p0 revision added
optional support for AArch32 at EL0.

TRM: https://developer.arm.com/documentati

[ARM] Add Cortex-A510 CPU for AArch32 (#118811)

This core was originally AArch64-only, but the r1p0 revision added
optional support for AArch32 at EL0.

TRM: https://developer.arm.com/documentation/101604/0103

show more ...

[llvm][ARM] Missing switch statement handles (#116086)

PR #115153 added enums which needed to be handled in a switch statement.
This trips up buildbot.

[ARM] Optimise non-ABI frame pointers (#110286)

With -fomit-frame-pointer, even if we set up a frame pointer for other
reasons (e.g. variable-sized or over-aligned stack allocations), we
don't nee

[ARM] Optimise non-ABI frame pointers (#110286)

With -fomit-frame-pointer, even if we set up a frame pointer for other
reasons (e.g. variable-sized or over-aligned stack allocations), we
don't need to create an ABI-compliant frame record. This means that we
can save all of the general-purpose registers in one push, instead of
splitting it to ensure that the frame pointer and link register are
adjacent on the stack, saving two instructions per function.

show more ...

Re-land: [ARM] Fix frame chains with M-profile PACBTI (#110285)

When using AAPCS-compliant frame chains with PACBTI return address
signing, there ware a number of bugs in the generation of the frame

Re-land: [ARM] Fix frame chains with M-profile PACBTI (#110285)

When using AAPCS-compliant frame chains with PACBTI return address
signing, there ware a number of bugs in the generation of the frame
pointer and function prologues. The most obvious was that we sometimes
would modify r11 before pushing it to the stack, so it wasn't preserved
as required by the PCS. We also sometimes did not push R11 and LR
adjacent to one another on the stack, or used R11 as a frame pointer
without pointing it at the saved value of R11, both of which are
required to have an AAPCS compliant frame chain.

The original work of this patch was done by James Westwood, reviewed as
#82801 and #81249, with some tidy-ups done by Mark Murray and myself.

show more ...

Revert "[ARM] Fix frame chains with M-profile PACBTI (#110285)"

Reverting because this is causing failures with MSan:
https://lab.llvm.org/buildbot/#/builders/169/builds/4378

This reverts commit e1

Revert "[ARM] Fix frame chains with M-profile PACBTI (#110285)"

Reverting because this is causing failures with MSan:
https://lab.llvm.org/buildbot/#/builders/169/builds/4378

This reverts commit e1f8f84acec05997893c305c78fbf7feecf44dd7.

show more ...

[ARM] Fix frame chains with M-profile PACBTI (#110285)

When using AAPCS-compliant frame chains with PACBTI return address
signing, there ware a number of bugs in the generation of the frame
pointe

[ARM] Fix frame chains with M-profile PACBTI (#110285)

When using AAPCS-compliant frame chains with PACBTI return address
signing, there ware a number of bugs in the generation of the frame
pointer and function prologues. The most obvious was that we sometimes
would modify r11 before pushing it to the stack, so it wasn't preserved
as required by the PCS. We also sometimes did not push R11 and LR
adjacent to one another on the stack, or used R11 as a frame pointer
without pointing it at the saved value of R11, both of which are
required to have an AAPCS compliant frame chain.

The original work of this patch was done by James Westwood, reviewed as
#82801 and #81249, with some tidy-ups done by Mark Murray and myself.

show more ...

[ARM] Tidy up stack frame strategy code (NFC) (#110283)

We have two different ways of splitting the pushes of callee-saved
registers onto the stack, controlled by the confusingly similar names
STI.s

[ARM] Tidy up stack frame strategy code (NFC) (#110283)

We have two different ways of splitting the pushes of callee-saved
registers onto the stack, controlled by the confusingly similar names
STI.splitFramePushPop() and STI.splitFramePointerPush(). This removes
those functions and replaces them with a single function which returns
an enum. This is in preparation for adding another value to that enum.

The original work of this patch was done by James Westwood, reviewed as
#82801 and #81249, with some tidy-ups done by Mark Murray and myself.

show more ...

[llvm][ARM][NFC] Renaming FeaturePrefLoopAlignment (#109932)

The feature 'FeaturePrefLoopAlignment' was misleading as it was used to
set the alignment of branch targets such as functions. Renamed t

[llvm][ARM][NFC] Renaming FeaturePrefLoopAlignment (#109932)

The feature 'FeaturePrefLoopAlignment' was misleading as it was used to
set the alignment of branch targets such as functions. Renamed to
FeaturePreferfBranchAlignment.

show more ...

[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC

Some targets only pass a TargetMachine & to their subtarget constructor
and require a static_cast to their

[ARM][Mips][PowerPC] Remove unnecessary static_cast creating GISel InstructionSelector. NFC

Some targets only pass a TargetMachine & to their subtarget constructor
and require a static_cast to their target-specific TargetMachine subclass
to create *InstructionSelector.

These 3 targets already have the correct TargetMachine subclass
reference so no cast is needed.

show more ...

[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-l

[CodeGen] Remove target SubRegLiveness flags (#95437)

This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget->enableSubRegLiveness()`
has been changed to `MRI->subRegLivenessEnabled()` to make sure the
option properly applies.

show more ...

[ARM] Add support for Cortex-R52+ (#94633)

Cortex-R52+ is an Armv8-R AArch32 CPU.

Technical Reference Manual for Cortex-R52+:
https://developer.arm.com/documentation/102199/latest/

[ARM][AArch64] autogenerate header file for TargetParser from Target tablegen files (#88378)

Introduce a mechanism to share data between the ARM and AArch64 backends and
TargetParser, to reduce dup

[ARM][AArch64] autogenerate header file for TargetParser from Target tablegen files (#88378)

Introduce a mechanism to share data between the ARM and AArch64 backends and
TargetParser, to reduce duplication of code. This is similar to the current
RISC-V implementation.

The target tablegen file (in this case `ARM.td` or `AArch64.td`) is
processed during building of `TargetParser` to generate the following
files in the build tree:
- `build/include/llvm/TargetParser/ARMTargetParserDef.inc`
- `build/include/llvm/TargetParser/AArch64TargetParserDef.inc`

For now, the use of these generated files is limited to files _outside_
of `TargetParser`. The main reason for this is that the modifications to
`TargetParser` will require additional data added to the tablegen files,
which I want to split into separate PRs.

show more ...

[NFC] Remove unused parameter from shouldAssumeDSOLocal()

Add support for Arm Cortex A78AE CPU (#84485)

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
https://developer.arm.com/documentation/101779/0003

Fixe

Add support for Arm Cortex A78AE CPU (#84485)

Add support for Arm Cortex A78AE CPU

Technical Reference Manual for Arm Cortex A78AE:
https://developer.arm.com/documentation/101779/0003

Fixes #84450

show more ...

Revert "[ARM] R11 not pushed adjacent to link register with PAC-M and… (#84019)

… AAPCS frame chain fix (#82801)"

This reverts commit 00e4a4197137410129d4725ffb82bae9ce44bdde. This patch
was fou

Revert "[ARM] R11 not pushed adjacent to link register with PAC-M and… (#84019)

… AAPCS frame chain fix (#82801)"

This reverts commit 00e4a4197137410129d4725ffb82bae9ce44bdde. This patch
was found to cause miscompilations and compilation failures.

show more ...

[ARM] R11 not pushed adjacent to link register with PAC-M and AAPCS frame chain fix (#82801)

When code for M class architecture was compiled with AAPCS and PAC
enabled, the frame pointer, r11, was

[ARM] R11 not pushed adjacent to link register with PAC-M and AAPCS frame chain fix (#82801)

When code for M class architecture was compiled with AAPCS and PAC
enabled, the frame pointer, r11, was not pushed to the stack adjacent to
the link register. Due to PAC being enabled, r12 was placed between r11
and lr. This patch fixes this by adding an extra case to the already
existing code that splits the GPR push in two when R11 is the frame
pointer and certain paremeters are met. The differential revision for
this previous change can be found here:
https://reviews.llvm.org/D125649. This now ensures that r11 and lr are
pushed in a separate push instruction to the other GPRs when PAC and
AAPCS are enabled, meaning the frame pointer and link register are now
pushed onto the stack adjacent to each other.

show more ...

[ARM] Simplify shouldAssumeDSOLocal for ELF. NFC

[ARM][AArch32] Add support for AArch32 Cortex-M52 CPU (#74822)

Cortex-M52 is an Armv8.1 AArch32 CPU.

Technical specifications available at:
https://developer.arm.com/processors/cortex-m52

[ARM] generate armv6m eXecute Only (XO) code

[ARM] generate armv6m eXecute Only (XO) code for immediates, globals

Previously eXecute Only (XO) support was implemented for targets that support
MOVW/

[ARM] generate armv6m eXecute Only (XO) code

[ARM] generate armv6m eXecute Only (XO) code for immediates, globals

Previously eXecute Only (XO) support was implemented for targets that support
MOVW/MOVT (~armv7+). See: https://reviews.llvm.org/D27449

XO prevents the compiler from generating data accesses to code sections. This
patch implements XO codegen for armv6-M, which does not support MOVW/MOVT, and
must resort to the following general pattern to avoid loads:

movs r3, :upper8_15:foo
lsls r3, #8
adds r3, :upper0_7:foo
lsls r3, #8
adds r3, :lower8_15:foo
lsls r3, #8
adds r3, :lower0_7:foo
ldr r3, [r3]

This is equivalent to the code pattern generated by GCC.

The above relocations are new to LLVM and have been implemented in a parent
patch: https://reviews.llvm.org/D149443.

This patch limits itself to implementing codegen for this pattern and enabling
XO for armv6-M in the backend.

Separate patches will follow for:
- switch tables
- replacing specific loads from constant islands which are spread out over the
ARM backend codebase. Amongst others: FastISel, call lowering, stack frames.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D152795

show more ...

[NFC][ARM][AArch64] Cleanup TargetParser includes

llvm/TargetParser/TargetParser.h now only includes AMDGPU-specific
functionality, the ARM- and AArch64-specific functionality is in other
headers.

[NFC][TargetParser] Remove llvm/ADT/Triple.h

I also ran `git clang-format` to get the headers in the right order for
the new location, which has changed the order of other headers in two
files.

[NFC][TargetParser] Remove llvm/Support/TargetParser.h

[NFC][TargetParser] Remove llvm/Support/ARMTargetParser.h

Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options