[NFC] Make AMDGPUCombinerHelper methods const (#121903)

(This replaces #121740. Sorry for wasting your time.)

This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: m

[NFC] Make AMDGPUCombinerHelper methods const (#121903)

(This replaces #121740. Sorry for wasting your time.)

This is a follow-up to a previous commit (ee7ca0d) which eliminated
several "TODO: make CombinerHelper methods const" remarks. As promised
in that ealier commit, this change completes the set by also making the
methods of AMDGPUCombinerHelper const so that the Helper member of
AMDGPUPreLegalizerCombinerImpl can be const rather than explicitly
mutable.

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[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)

This combine pattern perform the below transformation.

fmul x, select(y, A, B) -> fldexp (x, select i32 (y, a

[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)

This combine pattern perform the below transformation.

fmul x, select(y, A, B) -> fldexp (x, select i32 (y, a, b))
fmul x, select(y, -A, -B) -> fldexp ((fneg x), select i32 (y, a, b))

where, A=2^a & B=2^b ; a and b are integers.

It is a follow-up PR to implement the above combine for globalIsel, as
the corresponding DAG combine has been done for SelectionDAG Isel
(#111109)

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AMDGPU/GlobalISel: Use correct type for intrinsic ID

[AMDGPU] Remove unneeded calls to setInstrAndDebugLoc in matchers. NFC.

[AMDGPU] Min/max changes for GFX12 (#75214)

Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>

AMDGPU/GlobalISel: Don't pointlessly check for convergent intrinsics

The set of handled intrinsics for fneg combines aren't convergent. The only
case we might want to handle is mov_dpp.

[GlobalISel] convergent intrinsics

Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets tha

[GlobalISel] convergent intrinsics

Introduced the convergent equivalent of the existing G_INTRINSIC opcodes:

- G_INTRINSIC_CONVERGENT
- G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS

Out of the targets that currently have some support for GlobalISel, the patch
assumes that the convergent intrinsics only relevant to SPIRV and AMDGPU.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154766

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Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operan

Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.
Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.

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Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of th

Revert "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

This reverts commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa.

The changes did not cover all occurrences of the deteleted function
MachineInstr::getIntrinsicID().

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[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the i

[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR

Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic
ID is the first non-def operand to the instruction. These are now represented as
a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID()
is now moved to this subclass GIntrinsic.

Some target-defined instructions behave like GMIR intrinsics, and have an
Intrinsic::ID operand. But they should not be recognized as generic intrinsics,
and should not use GIntrinsic::getIntrinsicID(). Separated these out by
introducing a new AMDGPU::getIntrinsicID().

Reviewed By: arsenm, Pierre-vh

Differential Revision: https://reviews.llvm.org/D155556

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AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8

If we have legal f16 instructions but no f16 med3, we can save
one instruction by expanding out the min/max sequence compared
to casting

AMDGPU: Expand casted f16 fmed3 pattern to fmin/fmax on gfx8

If we have legal f16 instructions but no f16 med3, we can save
one instruction by expanding out the min/max sequence compared
to casting to f32 and casting back.

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[CodeGen] llvm::Optional => std::optional

[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine

Newly created fneg was built after some of it's uses in some cases.
Now it will be built immediately after instruction whose dst it nega

[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine

Newly created fneg was built after some of it's uses in some cases.
Now it will be built immediately after instruction whose dst it negates.

Differential Revision: https://reviews.llvm.org/D119459

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Remove redundant return and continue statements (NFC)

Identified with readability-redundant-control-flow.

Fix MSVC signed/unsigned mismatch warning. NFC.

[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods

If possible fold fneg into instruction above if users cannot fold mods and we
know it will decrease instruction count.
Follows same

[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods

If possible fold fneg into instruction above if users cannot fold mods and we
know it will decrease instruction count.
Follows same logic as SDAG combiner in choosing opportunities to combine.

Differential Revision: https://reviews.llvm.org/D112827

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