[CodeGen] RegisterCoalescer: Remove unused AliasAnalysis dependency (#124773)

[CodeGen][NFC] Format RegisterCoalescer sources (#124697)

Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)"

There's a regression with one of the bootstrap builds for x86.
I'll revert this while

Revert "Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)"

There's a regression with one of the bootstrap builds for x86.
I'll revert this while I investigate.

This reverts commit 4df6d3df24ae9cff07c70c96a1663cbba6e1dca5.

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Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)

This PR aims to reland work done by @arsenm which was previously
reverted due to some tangenti

Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" (#123632)

This PR aims to reland work done by @arsenm which was previously
reverted due to some tangentially related scheduler issues as discussed
on #76416.

This PR cherry-picks the original commit (0e46b49de433), and adds
another patch on top with the following changes:

* The code in `updateRegDefsUses` now updates subranges when
subreg-liveness-tracking is enabled.

* When adding an implicit-def operand for the super-register,
the code in `reMaterializeTrivialDef` which tries to remove
undefined subranges should now take into account that the lanes
from the super-reg are no longer undefined.

Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>

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[LLVM] Fix various cl::desc typos and whitespace issues (NFC) (#121955)

[Coalescer] Consider NewMI's subreg index when updating lanemask. (#121780)

The code added in #116191 that updated the lanemasks for rematerialized
values checked if `DefMI`'s destination register

[Coalescer] Consider NewMI's subreg index when updating lanemask. (#121780)

The code added in #116191 that updated the lanemasks for rematerialized
values checked if `DefMI`'s destination register had a subreg index.
This seems to have missed the following case:

```
%0:gpr32 = MOVi32imm 1
%1:gpr64 = SUBREG_TO_REG 0, %0:gpr32, %subreg.sub_32
```

which during rematerialization would have the following variables set:

```
DefMI = %0:gpr32 = MOVi32imm 1

NewMI = %3.sub_32:gpr64 = MOVi32imm 1 (rematerialized value)
```

When checking whether the lanemasks need to be generated, considering
whether DefMI's destination has a subreg index is insufficient, we
should look at DefMI's subreg index instead.

The added tests are a bit more involved, because I was not able to
reconstruct the issue without having some control flow in the test.
These tests come from actual reproducers.

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[Coalescer] Move code added in #116191 (#121779)

By moving the code a bit later, we can factor out some of the conditions
as those are now already tested.
This will also be useful when adding anot

[Coalescer] Move code added in #116191 (#121779)

By moving the code a bit later, we can factor out some of the conditions
as those are now already tested.
This will also be useful when adding another fix on top that uses
`NewMI`'s subreg index (to follow as a separate PR).

The change is intended to be NFC.

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RegisterCoalescer: Fix assert on remat to copy-to-physreg with subregs (#121734)

Do not try to rematerialize a super-register def used by a subregister
extract copy into a copy to a physical regist

RegisterCoalescer: Fix assert on remat to copy-to-physreg with subregs (#121734)

Do not try to rematerialize a super-register def used by a subregister
extract copy into a copy to a physical register if the other pieces of
the
full physreg are live at the rematerialization point. It would insert
the
super-register def at the rematerialization point, and assert since the
other half of the register was already live.

This is analagous to the undef subregister def handling above,
which handled the virtual register case.

Fixes #120970

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RegisterCoalescer: Set undef on full register uses when coalescing implicit_def (#118321)

Previously this would delete the IMPLICIT_DEF and not introduce the undef
flag on the use operand.

Fixes su

RegisterCoalescer: Set undef on full register uses when coalescing implicit_def (#118321)

Previously this would delete the IMPLICIT_DEF and not introduce the undef
flag on the use operand.

Fixes sub-issue found while reducing #109294

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RegisterCoalescer: Fix creating full / empty subrange on undef subreg use (#117936)

Reland "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)"

This patch can now reland after 318c69de52b6 relanded #114827.

This reverts commit 14a58a1390a72ba6c66606e58e86

Reland "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)"

This patch can now reland after 318c69de52b6 relanded #114827.

This reverts commit 14a58a1390a72ba6c66606e58e86425dcb902763.

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Revert "[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)" (#117367)

To pass tests with #117307 revert.

This reverts commit 3093b29b597b9a936a3e4d1c8bc4a7ccba8fc848.

[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)

In a situation like the following:

```
undef %2.subreg = INST %1 ; DefMI (rematerializable),

[RegisterCoalescer] Fix up subreg lanemasks after rematerializing. (#116191)

In a situation like the following:

```
undef %2.subreg = INST %1 ; DefMI (rematerializable),
; DefSubIdx = subreg
%3 = COPY %2 ; SrcIdx = DstIdx = 0
.... = SOMEINSTR %3, %2
```
there are no subranges for `%3` because the entire register is copied,
but after rematerialization the subrange of the rematerialized value
must be fixed up with the appropriate subranges for `.subreg`.

(To me this issue seemed a bit similar to the issue fixed by #96839, but
then related to rematerialization)

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llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness o

llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.

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LiveInterval: Make verify functions return bool (#109672)

This will allow the MachineVerifier to check these properties
instead of just asserting

[CodeGen] Use MachineInstr::all_defs (NFC) (#106017)

[CodeGen] Remove AA parameter of isSafeToMove (#100691)

This `AA` parameter is not used and for most uses they just pass
a nullptr.

The use of `AA` was removed since 8d0383e.

[RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (#96839)

The issue with the handling of the SUBREG_TO_REG is that we don't join
the subranges correctly when we join live ra

[RegisterCoalescer] Fix SUBREG_TO_REG handling in the RegisterCoalescer. (#96839)

The issue with the handling of the SUBREG_TO_REG is that we don't join
the subranges correctly when we join live ranges across the
SUBREG_TO_REG. For example when joining across this:
```
32B %2:gr64_nosp = SUBREG_TO_REG 0, %0:gr32, %subreg.sub_32bit
```
we want to join these live ranges:
```
%0 [16r,32r:0) 0@16r weight:0.000000e+00
%2 [32r,112r:0) 0@32r weight:0.000000e+00
```
Before the fix the range for the resulting merged `%2` is:
```
%2 [16r,112r:0) 0@16r weight:0.000000e+00
```
After the fix it is now this:
```
%2 [16r,112r:0) 0@16r L000000000000000F [16r,112r:0) 0@16r weight:0.000000e+00
```

Two tests are added to this fix. The X86 test fails without the patch.
The PowerPC test passes with and without the patch but is added as a way
track future possible failures when register classes are changed in a
future patch.

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[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use

[CodeGen][NewPM] Port `LiveIntervals` to new pass manager (#98118)

- Add `LiveIntervalsAnalysis`.
- Add `LiveIntervalsPrinterPass`.
- Use `LiveIntervalsWrapperPass` in legacy pass manager.
- Use `std::unique_ptr` instead of raw pointer for `LICalc`, so
destructor and default move constructor can handle it correctly.

This would be the last analysis required by `PHIElimination`.

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[CodeGen][NewPM] Port `SlotIndexes` to new pass manager (#97941)

- Add `SlotIndexesAnalysis`.
- Add `SlotIndexesPrinterPass`.
- Use `SlotIndexesWrapperPass` in legacy pass.

[CodeGen][NewPM] Port `machine-loops` to new pass manager (#97793)

- Add `MachineLoopAnalysis`.
- Add `MachineLoopPrinterPass`.
- Convert to `MachineLoopInfoWrapperPass` in legacy pass manager.

[CodeGen] Use range-based for loops (NFC) (#96777)

[llvm] Use llvm::unique (NFC) (#95628)

RegisterCoalescer: Remove unnecessary maybe_unused

2214026e957397cc6385f778b28d570485a31856 didn't fix an unused variable
warning correctly.

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

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