Revert "Don't check liveness of unallocatable registers."

The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548

Don't check liveness of unallocatable registers.

This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be all

Don't check liveness of unallocatable registers.

This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

llvm-svn: 136541

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Check for multiple defs in the machine code verifier.

llvm-svn: 136535

- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo

- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

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More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

llvm-svn: 133944

Use TRI::has{Sub,Super}ClassEq() where possible.

No functional change.

llvm-svn: 132455

Revert r128961 because it didn't include a test and causes the verifier to fail
on CodeGen/X86/2007-05-07-InvokeSRet.ll. There is probably a bug here that was
fixed by r128961, but since there is no

Revert r128961 because it didn't include a test and causes the verifier to fail
on CodeGen/X86/2007-05-07-InvokeSRet.ll. There is probably a bug here that was
fixed by r128961, but since there is no test or reference to a source file I have
to revert it.

llvm-svn: 131618

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SjLj EH could produce a machine basic block that legitimately has more than one
landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's g

SjLj EH could produce a machine basic block that legitimately has more than one
landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>

llvm-svn: 130881

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Permit blocks to branch directly to a landing pad.

Treat the landing pad as a normal successor when that happens.

llvm-svn: 128961

Allow kill flags on two-address instructions. They are harmless.

llvm-svn: 128643

Mark all uses as <undef> when joining a copy.

This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Mark all uses as <undef> when joining a copy.

This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

llvm-svn: 128642

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Verify kill flags conservatively.

Allow a live range to end with a kill flag, but don't allow a kill flag that
doesn't end the live range.

This makes the machine code verifier more useful during re

Verify kill flags conservatively.

Allow a live range to end with a kill flag, but don't allow a kill flag that
doesn't end the live range.

This makes the machine code verifier more useful during register allocation when
kill flag computation is deferred.

llvm-svn: 124838

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Verify slot index ordering.

The slot indexes must be monotonically increasing through the function.

llvm-svn: 123324

Verify that machine instruction parent pointers are consistent.

llvm-svn: 123322

Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first vi

Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107

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Fix a MachineVerifier loop that probably didn't mean to skip the last two
virtual registers.

llvm-svn: 123100

Simplify some code in MachineVerifier that was doing the correct thing, but not
in the most obvious way.

llvm-svn: 122610

Add knowledge of phi-def and phi-kill valnos to MachineVerifier's predecessor
valno verification. The "Different value live out of predecessor" check is
incorrect in the case of phi-def valnos, so ju

Add knowledge of phi-def and phi-kill valnos to MachineVerifier's predecessor
valno verification. The "Different value live out of predecessor" check is
incorrect in the case of phi-def valnos, so just skip that check for phi-def
valnos and instead check that all of the valnos for predecessors have phi-kill.
Fixes PR8863.

llvm-svn: 122581

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MachineVerifier should count landing pad successors as basic blocks rather than
out-edges. Fixes PR8824.

llvm-svn: 122228

Teach MachineVerifier that early clobber defs begin at USE slots and other defs
begin at DEF slots. Fixes the second half of PR8813.

llvm-svn: 122225

Add a missing check from r122218.

llvm-svn: 122224

Don't assume that an instruction ending a register's live range always reads
the register; it may be a dead def instead. Fixes PR8820.

llvm-svn: 122218

Ignore debug values when performing MachineVerifier liveness checks. Fixes
PR8822.

llvm-svn: 122207

Early clobber operands are allowed to be defined at use indices. This fixes one
half of PR8813.

llvm-svn: 122205

Fix PR8811 by teaching MachineVerifier about optional defs.

llvm-svn: 122199