Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator

llvm-svn: 158154

Properly verify liveness with bundled machine instructions.

Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
b

Properly verify liveness with bundled machine instructions.

Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
bundles.

llvm-svn: 158116

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Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in

Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854

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Optional def can be either a def or a use (of reg0).

llvm-svn: 157640

Fix a verifier bug.

Make sure useless (def-only) intervals also get verified.

llvm-svn: 157000

Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_r

Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

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Enable machine code verification after PreSched2 passes.

The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax th

Enable machine code verification after PreSched2 passes.

The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

llvm-svn: 153614

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Skip liveness verification when MRI->tracksLiveness() is false.

Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
informa

Skip liveness verification when MRI->tracksLiveness() is false.

Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

llvm-svn: 153596

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Report the defining instruction.

llvm-svn: 152460

Add SSA verification to MachineVerifier.

Somehow we never verified SSA dominance before.

llvm-svn: 152458

Use SmallPtrSet instead of DenseSet.

llvm-svn: 152457

Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

llvm-svn: 152016

Move the operand iterator into MachineInstrBundle.h where it belongs.

Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This elimin

Move the operand iterator into MachineInstrBundle.h where it belongs.

Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This eliminates the mystery bool constructor argument.

llvm-svn: 151684

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Handle regmasks in the machine code verifier.

llvm-svn: 151607

Update machine code verifier.

After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live inter

Update machine code verifier.

After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

llvm-svn: 151531

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Update MachineVerifier to check the new physreg live-in rules.

llvm-svn: 150496

- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruct

- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.

llvm-svn: 146542

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Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayL

Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

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Remove all remaining uses of Value::getNameStr().

llvm-svn: 144648

Use getVNInfoBefore() when it makes sense.

llvm-svn: 144517

Rename SlotIndexes to match how they are used.

The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

Th

Rename SlotIndexes to match how they are used.

The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals. In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used. This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

llvm-svn: 144503

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Fix sub-register operand verification.

PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register cla

Fix sub-register operand verification.

PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register class support the sub-reg index.

llvm-svn: 141220

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Verify that terminators follow non-terminators.

This exposes a -segmented-stacks bug.

llvm-svn: 140429

Lower ARM adds/subs to add/sub after adding optional CPSR operand.

This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
stra

Lower ARM adds/subs to add/sub after adding optional CPSR operand.

This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228

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Stop verifying hasPHIKill() flags.

There is only one legitimate use remaining, in addIntervalsForSpills().
All other calls to hasPHIKill() are only used to update PHIKill flags.

The addIntervalsFor

Stop verifying hasPHIKill() flags.

There is only one legitimate use remaining, in addIntervalsForSpills().
All other calls to hasPHIKill() are only used to update PHIKill flags.

The addIntervalsForSpills() function is part of the old spilling
framework, only used by linearscan.

llvm-svn: 139783

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