MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.

The PATCHPOINT instructions have a single optional defined register operand,
but the machine verifier can't verify the o

MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.

The PATCHPOINT instructions have a single optional defined register operand,
but the machine verifier can't verify the optional defined register operands.
This commit makes sure that the machine verifier won't report an error when a
PATCHPOINT instruction doesn't have its optional defined register operand.
This change will allow us to enable the machine verifier for the code
generation tests for the patchpoint intrinsics.

Reviewers: Juergen Ributzka
llvm-svn: 244513

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LiveInterval: Document and enforce rules about empty subranges.

Empty subranges are not allowed in a LiveInterval and must be removed
instead: Check this in the verifiers, put a reminder for this in

LiveInterval: Document and enforce rules about empty subranges.

Empty subranges are not allowed in a LiveInterval and must be removed
instead: Check this in the verifiers, put a reminder for this in the
comment of the shrinkToUses variant for a single lane and make it
automatic for the shrinkToUses variant for a LiveInterval.

llvm-svn: 242431

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Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)

Apparently, the style needs to be agreed upon first.

llvm-svn: 240390

Fixed/added namespace ending comments using clang-tidy. NFC

The patch is generated using this command:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-c

Fixed/added namespace ending comments using clang-tidy. NFC

The patch is generated using this command:

tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \
llvm/lib/


Thanks to Eugene Kosov for the original patch!

llvm-svn: 240137

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MachineFrameInfo: Simplify pristine register calculation.

About pristine regsiters:
Pristine registers "hold a value that is useless to the current
function, but that must be preserved - they are ca

MachineFrameInfo: Simplify pristine register calculation.

About pristine regsiters:
Pristine registers "hold a value that is useless to the current
function, but that must be preserved - they are callee saved registers
that have not been saved." This concept saves compile time as it frees
the prologue/epilogue inserter from adding every such register to every
basic blocks live-in list.

However the current code in getPristineRegs is formulated in a
complicated way: Inside the function prologue and epilogue all callee
saves are considered pristine, while in the rest of the code only the
non-saved ones are considered pristine. This requires logic to
differentiate between prologue/epilogue and the rest and in the presence
of shrink-wrapping this even becomes complicated/expensive. It's also
unnecessary because the prologue epilogue inserters already mark
callee-save registers that are saved/restores properly in the respective
blocks in the prologue/epilogue (see updateLiveness() in
PrologueEpilogueInserter.cpp). So only declaring non-saved/restored
callee saved registers as pristine just works.

Differential Revision: http://reviews.llvm.org/D10101

llvm-svn: 238524

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MachineInstr: Change return value of getOpcode() to unsigned.

This was previously returning int. However there are no negative opcode
numbers and more importantly this was needlessly different from

MachineInstr: Change return value of getOpcode() to unsigned.

This was previously returning int. However there are no negative opcode
numbers and more importantly this was needlessly different from
MCInstrDesc::getOpcode() (which even is the value returned here) and
SDValue::getOpcode()/SDNode::getOpcode().

llvm-svn: 237611

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Fix typo

llvm-svn: 236283

MachineVerifier: Don't crash if MachineOperand has no parent

If you somehow added a MachineOperand to an instruction
that did not have the parent set, the verifier would
crash since it attempts to u

MachineVerifier: Don't crash if MachineOperand has no parent

If you somehow added a MachineOperand to an instruction
that did not have the parent set, the verifier would
crash since it attempts to use the operand's parent.

llvm-svn: 236249

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MachineVerifier: slightly simplify code that is only called with vregs

llvm-svn: 233216

Do not track subregister liveness when it brings no benefits

Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multip

Do not track subregister liveness when it brings no benefits

Some subregisters are only to indicate different access sizes, while not
providing any way to actually divide the register up into multiple
disjunct parts. Avoid tracking subregister liveness in these cases as it
is not beneficial.

Differential Revision: http://reviews.llvm.org/D8429

llvm-svn: 232695

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[llvm] Replacing asserts with static_asserts where appropriate

Summary:
This patch consists of the suggestions of clang-tidy/misc-static-assert check.


Reviewers: alexfh

Reviewed By: alexfh

Subsc

[llvm] Replacing asserts with static_asserts where appropriate

Summary:
This patch consists of the suggestions of clang-tidy/misc-static-assert check.


Reviewers: alexfh

Reviewed By: alexfh

Subscribers: xazax.hun, llvm-commits

Differential Revision: http://reviews.llvm.org/D8343

llvm-svn: 232366

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Have TargetRegisterInfo::getLargestLegalSuperClass take a
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

llvm-svn: 231888

Rewrite MachineOperand::print and MachineInstr::print to avoid
uses of TM->getSubtargetImpl and propagate to all calls.

This could be a debugging regression in places where we had a
TargetMachine an

Rewrite MachineOperand::print and MachineInstr::print to avoid
uses of TM->getSubtargetImpl and propagate to all calls.

This could be a debugging regression in places where we had a
TargetMachine and/or MachineFunction but don't have it as part
of the MachineInstr. Fixing this would require passing a
MachineFunction/Function down through the print operator, but
none of the existing uses in tree seem to do this.

llvm-svn: 230710

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Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.

This preserves the handy fu

Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.

This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications.

llvm-svn: 228079

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MachineVerifier: Allow undef reads if a matching superreg is defined.

Summary:
Some pseudo instruction expansions break down a wide register use into
multiple uses of smaller sub registers. If the s

MachineVerifier: Allow undef reads if a matching superreg is defined.

Summary:
Some pseudo instruction expansions break down a wide register use into
multiple uses of smaller sub registers. If the super register was
partially undefined the broken down sub registers may be completely
undefined now leading to MachineVerifier complaints. Unfortunately
liveness information to add the required dead flags is not easily
(cheaply) available when expanding pseudo instructions.

This commit changes the verifier to be quiet if there is an additional
implicit use of a super register. Pseudo instruction expanders can use
this to mark cases where partially defined values get potentially broken
into completely undefined ones.

Differential Revision: http://reviews.llvm.org/D6973

llvm-svn: 226047

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[CodeGen] Let MachineVerifierPass own its banner string

llvm-svn: 224041

LiveInterval: Use range based for loops for subregister ranges.

llvm-svn: 223991

LiveInterval: Use more range based for loops for value numbers and segments.

llvm-svn: 223978

MachineVerifier: Allow physreg use if just a subreg is defined.

We can't mark partially undefined registers, so we have to allow reading
a register in the machine verifier if just parts of a registe

MachineVerifier: Allow physreg use if just a subreg is defined.

We can't mark partially undefined registers, so we have to allow reading
a register in the machine verifier if just parts of a register are
defined.

llvm-svn: 223896

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MachineVerifier: Allow LiveInterval segments to end at a partial write.

In the subregister liveness tracking case we do not create implicit
reads on partial register writes anymore, still we need to

MachineVerifier: Allow LiveInterval segments to end at a partial write.

In the subregister liveness tracking case we do not create implicit
reads on partial register writes anymore, still we need to produce a new
SSA value for partial writes so the live segment has to end.

llvm-svn: 223895

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LiveInterval: Add support to track liveness of subregisters.

This code adds the required data structures. Algorithms to compute it follow.

llvm-svn: 223877

[MachineVerifier] Accept a MBB with a single landing pad successor.

The MachineVerifier used to check that there was always exactly one
unconditional branch to a non-landingpad (normal) successor.
I

[MachineVerifier] Accept a MBB with a single landing pad successor.

The MachineVerifier used to check that there was always exactly one
unconditional branch to a non-landingpad (normal) successor.
If that normal successor to an invoke BB is unreachable, it seems
reasonable to only have one successor, the landing pad.
On targets other than AArch64 (and on AArch64 with a different testcase),
the branch folder turns the branch to the landing pad into a fallthrough.
The MachineVerifier, which relies on AnalyzeBranch, is unable to check
the condition, and doesn't complain. However, it does in this specific
testcase, where the branch to the landing pad remained.
Make the MachineVerifier accept it.

llvm-svn: 223059

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MachineVerifier: Report register for bad liveranges

llvm-svn: 222380

Move register class name strings to a single array in MCRegisterInfo to reduce static table size and number of relocation entries.

Indices into the table are stored in each MCRegisterClass instead o

Move register class name strings to a single array in MCRegisterInfo to reduce static table size and number of relocation entries.

Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table.

llvm-svn: 222118

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Access subtarget specific variables off of the MachineFunction's
cached subtarget and not the TargetMachine.

llvm-svn: 219668