MachineVerifier: On dead-def live segments, check that corresponding machine operand has a dead flag

llvm-svn: 264769

Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty

Summary:
Check that any function that has the property set is free of virtual
register operands.

Also, it is actually VirtReg

Add MachineVerifier check for AllVRegsAllocated MachineFunctionProperty

Summary:
Check that any function that has the property set is free of virtual
register operands.

Also, it is actually VirtRegMap (and not the register allocators) that
acutally remove the VReg operands (except for RegAllocFast).

Reviewers: qcolombet

Subscribers: MatzeB, llvm-commits, qcolombet

Differential Revision: http://reviews.llvm.org/D18535

llvm-svn: 264755

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WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC

Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null. Besid

WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC

Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null. Besides
being a nice cleanup, this is tacking toward a fix for PR26753.

llvm-svn: 262141

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CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC

Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals. The MachineInstrs

CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC

Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are
never null, so this cleans up the API a bit. It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).

At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.

llvm-svn: 262115

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CodeGen: TII: Take MachineInstr& in predicate API, NFC

Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to

CodeGen: TII: Take MachineInstr& in predicate API, NFC

Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest). All of these
functions require non-null parameters already, so references are more
clear. As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.

No functionality change intended.

llvm-svn: 261605

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ADT: Remove == and != comparisons between ilist iterators and pointers

I missed == and != when I removed implicit conversions between iterators
and pointers in r252380 since they were defined outsid

ADT: Remove == and != comparisons between ilist iterators and pointers

I missed == and != when I removed implicit conversions between iterators
and pointers in r252380 since they were defined outside ilist_iterator.

Since they depend on getNodePtrUnchecked(), they indirectly rely on UB.
This commit removes all uses of these operators. (I'll delete the
operators themselves in a separate commit so that it can be easily
reverted if necessary.)

There should be NFC here.

llvm-svn: 261498

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MachineVerifier: Add parameter to choose if MachineFunction::verify() aborts

The abort on error behaviour is unpractical for debugger and unittest
usage.

llvm-svn: 260904

MachineVerifier: Check that defs/uses are live in subregisters as well.

llvm-svn: 259552

MachineVerifier: Use report_context() instead of ad-hoc messages.

llvm-svn: 259457

LiveInterval: A LiveRange is enough for ConnectedVNInfoEqClasses::Classify()

llvm-svn: 257129

Move EH-specific helper functions to a more appropriate place

No functionality change is intended.

llvm-svn: 254562

MachineVerifier: Streamline live interval related error reporting

Simply perform additional report_context() calls after a report()
instead of adding more and more overloaded variations of report().

MachineVerifier: Streamline live interval related error reporting

Simply perform additional report_context() calls after a report()
instead of adding more and more overloaded variations of report(). Also
improve several instances where information was output in an ad-hoc way
probably because no matching report() overload was available.

llvm-svn: 252552

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MachineVerifier: Add missing linebreak

MachineInstr::print() with SkipOppers==true does not produce a
linebreak, so we have to do that in MachineVerifier::report().

llvm-svn: 252551

MachineVerifier: MI::print has no TargetMachine overload

The code was passing a target machine pointer which degraded to a true
operand to SkipOppers.

llvm-svn: 252550

MachineVerifier: print list of live intervals if available

llvm-svn: 252549

[WinEH] Tweak funclet prologue/epilogue insertion to pass verifier

For some reason we'd never run MachineVerifier on WinEH code, and you
explicitly have to ask for it with llc. I added it to a few t

[WinEH] Tweak funclet prologue/epilogue insertion to pass verifier

For some reason we'd never run MachineVerifier on WinEH code, and you
explicitly have to ask for it with llc. I added it to a few test cases
to get some coverage.

Fixes PR25461.

llvm-svn: 252512

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[MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.

Since the verifier will give false reports if it incorrectly thinks MI is
loading or storing using an FI, it is necessary to scan m

[MachineVerifier] Analyze MachineMemOperands for mem-to-mem moves.

Since the verifier will give false reports if it incorrectly thinks MI is
loading or storing using an FI, it is necessary to scan memoperands and
find out how the FI is used in the instruction. This should be relatively
rare.

Needed to make CodeGen/SystemZ/spill-01.ll pass, which now runs with this flag.

Reviewed by Quentin Colombet.

llvm-svn: 251620

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Let MachineVerifier be aware of mem-to-mem instructions.

A mem-to-mem instruction (that both loads and stores), which store to an
FI, cannot pass the verifier since it thinks it is loading from the

Let MachineVerifier be aware of mem-to-mem instructions.

A mem-to-mem instruction (that both loads and stores), which store to an
FI, cannot pass the verifier since it thinks it is loading from the FI.

For the mem-to-mem instruction, do a looser check in visitMachineOperand()
and only check liveness at the reg-slot while analyzing a frame index operand.

Needed to make CodeGen/SystemZ/xor-01.ll pass with -verify-machineinstrs,
which now runs with this flag.

Reviewed by Evan Cheng and Quentin Colombet.

llvm-svn: 250885

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CodeGen: Continue removing ilist iterator implicit conversions

llvm-svn: 249884

TargetRegisterInfo: Introduce PrintLaneMask.

This makes it more convenient to print lane masks and lead to more
uniform printing.

llvm-svn: 248624

TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC

llvm-svn: 248623

Save LaneMask with livein registers

With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only

Save LaneMask with livein registers

With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only keeps registers in the live-in list and therefore
enumerated all subregisters affected by the lanemask. This turned out to
be too conservative as the subregister may also cover additional parts
of the lanemask which are not live. Expressing a given lanemask by
enumerating a minimum set of subregisters is computationally expensive
so the best solution is to simply change the live-in list to store the
lanemasks as well. This will reduce memory usage for targets using
subregister liveness and slightly increase it for other targets

Differential Revision: http://reviews.llvm.org/D12442

llvm-svn: 247171

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MachineVerifier: Check that SlotIndex MBBIndexList is sorted.

This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commi

MachineVerifier: Check that SlotIndex MBBIndexList is sorted.

This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commit.

llvm-svn: 247166

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[WinEH] Add some support for code generating catchpad

We can now run 32-bit programs with empty catch bodies. The next step
is to change PEI so that we get funclet prologues and epilogues.

llvm-sv

[WinEH] Add some support for code generating catchpad

We can now run 32-bit programs with empty catch bodies. The next step
is to change PEI so that we get funclet prologues and epilogues.

llvm-svn: 246235

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MachineBasicBlock: Add liveins() method returning an iterator_range

llvm-svn: 245895