#
5022fc2a |
| 24-May-2023 |
Jay Foad <jay.foad@amd.com> |
[CodeGen] Make use of MachineInstr::all_defs and all_uses. NFCI.
Differential Revision: https://reviews.llvm.org/D151424
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Revision tags: llvmorg-16.0.4 |
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#
64599ac9 |
| 12-May-2023 |
Jonas Paulsson <paulsson@linux.vnet.ibm.com> |
[MachineSink] Don't reject sinking because of dead def in isProfitableToSinkTo().
An instruction should be sunk (if otherwise legal and profitable) regardless of if it has a dead def of a physreg or
[MachineSink] Don't reject sinking because of dead def in isProfitableToSinkTo().
An instruction should be sunk (if otherwise legal and profitable) regardless of if it has a dead def of a physreg or not. Physreg defs are checked in other places and sinking is only done with dead defs of regs that are not live into the target MBB.
Differential Revision: https://reviews.llvm.org/D150447
Reviewed By: sebastian-ne, arsenm
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Revision tags: llvmorg-16.0.3, llvmorg-16.0.2 |
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#
14bc3748 |
| 17-Apr-2023 |
Jay Foad <jay.foad@amd.com> |
[MC] Use subregs/superregs instead of MCSubRegIterator/MCSuperRegIterator. NFC.
Differential Revision: https://reviews.llvm.org/D148613
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#
8bf7f86d |
| 17-Apr-2023 |
Akshay Khadse <akshayskhadse@gmail.com> |
Fix uninitialized pointer members in CodeGen
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.
Reviewed By: LuoYuanke
Differentia
Fix uninitialized pointer members in CodeGen
This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D148303
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Revision tags: llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2 |
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#
d170a254 |
| 03-Feb-2023 |
Jay Foad <jay.foad@amd.com> |
[CodeGen] Define and use MachineOperand::getOperandNo
This is a helper function to very slightly simplify many calls to MachineInstruction::getOperandNo.
Differential Revision: https://reviews.llvm
[CodeGen] Define and use MachineOperand::getOperandNo
This is a helper function to very slightly simplify many calls to MachineInstruction::getOperandNo.
Differential Revision: https://reviews.llvm.org/D143250
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Revision tags: llvmorg-16.0.0-rc1, llvmorg-17-init |
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#
e72ca520 |
| 13-Jan-2023 |
Craig Topper <craig.topper@sifive.com> |
[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D141715
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Revision tags: llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1 |
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#
e10e9363 |
| 15-Sep-2022 |
Stephen Tozer <Stephen.Tozer@Sony.com> |
[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation, which result in different MIR output but ident
[DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation, which result in different MIR output but identical final DWARF output (NFC w.r.t. the full compilation). The two changes are:
* The introduction of a new MachineOperand type, MO_DbgInstrRef, which consists of two unsigned numbers that are used to index an instruction and an output operand within that instruction, having a meaning identical to first two operands of the current DBG_INSTR_REF instruction. This operand is only used in DBG_INSTR_REF (see below). * A change in syntax for the DBG_INSTR_REF instruction, shuffling the operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE, and replacing the first two operands with a single MO_DbgInstrRef-type operand.
This patch is the first of a set that will allow DBG_INSTR_REF instructions to refer to multiple machine locations in the same manner as DBG_VALUE_LIST.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D129372
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Revision tags: llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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#
9e6d1f4b |
| 17-Jul-2022 |
Kazu Hirata <kazu@google.com> |
[CodeGen] Qualify auto variables in for loops (NFC)
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#
874fbe2c |
| 24-Jun-2022 |
Carl Ritson <carl.ritson@amd.com> |
[MachineSink] Clear kill flags on operands outside loop
If an instruction is sunk into a loop then any kill flags on operands declared outside the loop must be cleared as these will be live for all
[MachineSink] Clear kill flags on operands outside loop
If an instruction is sunk into a loop then any kill flags on operands declared outside the loop must be cleared as these will be live for all loop iterations.
Fixes #46827
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D126754
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Revision tags: llvmorg-14.0.6 |
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#
3815ae29 |
| 21-Jun-2022 |
Markus Lavin <markus.lavin@ericsson.com> |
[machinesink] fix debug invariance issue
Do not include debug instructions when comparing block sizes with thresholds.
Differential Revision: https://reviews.llvm.org/D127208
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#
16547f9f |
| 15-Jun-2022 |
Luo, Yuanke <yuanke.luo@intel.com> |
[CodeGen] Fix the bug of machine sink
The use operand may be undefined. In that case we can just continue to check the next operand since it won't increase register pressure.
Differential Revision:
[CodeGen] Fix the bug of machine sink
The use operand may be undefined. In that case we can just continue to check the next operand since it won't increase register pressure.
Differential Revision: https://reviews.llvm.org/D127848
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Revision tags: llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2 |
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#
d7927523 |
| 19-Apr-2022 |
Chen Zheng <czhengsz@cn.ibm.com> |
[MachineSink] replace MachineLoop with MachineCycle
reapply 62a9b36fcf728b104ea87e6eb84c0be69b779df7 and fix module build failue: 1: remove MachineCycleInfoWrapperPass in MachinePassRegistry.def
[MachineSink] replace MachineLoop with MachineCycle
reapply 62a9b36fcf728b104ea87e6eb84c0be69b779df7 and fix module build failue: 1: remove MachineCycleInfoWrapperPass in MachinePassRegistry.def MachineCycleInfoWrapperPass is a anylysis pass, should not be there. 2: move the definition for MachineCycleInfoPrinterPass to cpp file.
Otherwise, there are module conflicit for MachineCycleInfoWrapperPass in MachinePassRegistry.def and MachineCycleAnalysis.h after 62a9b36fcf728b104ea87e6eb84c0be69b779df7.
MachineCycle can handle irreducible loop. Natural loop analysis (MachineLoop) can not return correct loop depth if the loop is irreducible loop. And MachineSink is sensitive to the loop depth, see MachineSinking::isProfitableToSinkTo().
This patch tries to use MachineCycle so that we can handle irreducible loop better.
Reviewed By: sameerds, MatzeB
Differential Revision: https://reviews.llvm.org/D123995
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#
80c4910f |
| 25-May-2022 |
Chen Zheng <czhengsz@cn.ibm.com> |
Revert "[MachineSink] replace MachineLoop with MachineCycle"
This reverts commit 62a9b36fcf728b104ea87e6eb84c0be69b779df7. Cause build failure on lldb incremental buildbot: https://green.lab.llvm.or
Revert "[MachineSink] replace MachineLoop with MachineCycle"
This reverts commit 62a9b36fcf728b104ea87e6eb84c0be69b779df7. Cause build failure on lldb incremental buildbot: https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/43994/changes
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#
62a9b36f |
| 19-Apr-2022 |
Chen Zheng <czhengsz@cn.ibm.com> |
[MachineSink] replace MachineLoop with MachineCycle
MachineCycle can handle irreducible loop. Natural loop analysis (MachineLoop) can not return correct loop depth if the loop is irreducible loop. A
[MachineSink] replace MachineLoop with MachineCycle
MachineCycle can handle irreducible loop. Natural loop analysis (MachineLoop) can not return correct loop depth if the loop is irreducible loop. And MachineSink is sensitive to the loop depth, see MachineSinking::isProfitableToSinkTo().
This patch tries to use MachineCycle so that we can handle irreducible loop better.
Reviewed By: sameerds, MatzeB
Differential Revision: https://reviews.llvm.org/D123995
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Revision tags: llvmorg-14.0.1 |
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#
8e64d849 |
| 22-Mar-2022 |
Carl Ritson <carl.ritson@amd.com> |
[MachineSink] Check block prologue interference
Sinking must check for interference between the block prologue and the instruction being sunk. Specifically check for clobbering of uses by the prolog
[MachineSink] Check block prologue interference
Sinking must check for interference between the block prologue and the instruction being sunk. Specifically check for clobbering of uses by the prologue, and overwrites to prologue defined registers by the sunk instruction.
Reviewed By: rampitec, ruiling
Differential Revision: https://reviews.llvm.org/D121277
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#
989f1c72 |
| 15-Mar-2022 |
serge-sans-paille <sguelton@redhat.com> |
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in
Cleanup codegen includes
This is a (fixed) recommit of https://reviews.llvm.org/D121169
after: 1061034926 before: 1063332844
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121681
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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#
a278250b |
| 10-Mar-2022 |
Nico Weber <thakis@chromium.org> |
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https:/
Revert "Cleanup codegen includes"
This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20. Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang, and many LLVM tests, see comments on https://reviews.llvm.org/D121169
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#
7f230fee |
| 07-Mar-2022 |
serge-sans-paille <sguelton@redhat.com> |
Cleanup codegen includes
after: 1061034926 before: 1063332844
Differential Revision: https://reviews.llvm.org/D121169
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Revision tags: llvmorg-14.0.0-rc2 |
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#
6fde0439 |
| 24-Feb-2022 |
Nikita Popov <npopov@redhat.com> |
[MachineSink] Disable if there are any irreducible cycles
This is an alternative to D120330, which disables MachineSink for functions with irreducible cycles entirely. This avoids both the correctne
[MachineSink] Disable if there are any irreducible cycles
This is an alternative to D120330, which disables MachineSink for functions with irreducible cycles entirely. This avoids both the correctness problem, and ensures we don't perform non-profitable sinks into cycles. At the same time, it may also disable profitable sinks in the same function. This can be made more precise by using MachineCycleInfo in the future.
Fixes https://github.com/llvm/llvm-project/issues/53990.
Differential Revision: https://reviews.llvm.org/D120800
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#
ef949ecb |
| 16-Feb-2022 |
Carl Ritson <carl.ritson@amd.com> |
[MachineSink] Use SkipPHIsAndLabels for sink insertion points
For AMDGPU the insertion point for a block may not be the first non-PHI instruction. This happens when a block contains EXEC mask manip
[MachineSink] Use SkipPHIsAndLabels for sink insertion points
For AMDGPU the insertion point for a block may not be the first non-PHI instruction. This happens when a block contains EXEC mask manipulation related to control flow (converging lanes).
Use SkipPHIsAndLabels to determine the block insertion point so that the target can skip any block prologue instructions.
Reviewed By: rampitec, ruiling
Differential Revision: https://reviews.llvm.org/D119399
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#
bee4531b |
| 12-Feb-2022 |
Benjamin Kramer <benny.kra@googlemail.com> |
[MachineSink] Inline getRegUnits
Reg unit sets are uniqued, so no need to wrap it in a set.
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Revision tags: llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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#
10ed1eca |
| 18-Jan-2022 |
Vang Thao <vang.thao@amd.com> |
[MachineSink] Allow sinking of constant or ignorable physreg uses
For AMDGPU, any use of the physical register EXEC prevents sinking even if it is not a real physical register read. Add check to see
[MachineSink] Allow sinking of constant or ignorable physreg uses
For AMDGPU, any use of the physical register EXEC prevents sinking even if it is not a real physical register read. Add check to see if a physical register use can be ignored for sinking.
Also perform same constant and ignorable physical register check when considering sinking in loops.
https://reviews.llvm.org/D116053
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Revision tags: llvmorg-13.0.1-rc2 |
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#
bfd5dd15 |
| 25-Nov-2021 |
Kazu Hirata <kazu@google.com> |
[llvm] Use range-based for loops (NFC)
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Revision tags: llvmorg-13.0.1-rc1 |
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#
4e94e25c |
| 11-Nov-2021 |
Markus Lavin <markus.lavin@ericsson.com> |
Fix minor deficiency in machine-sink.
Register uses that are MRI->isConstantPhysReg() should not inhibit sinking transformation.
Reviewed By: StephenTozer
Differential Revision: https://reviews.ll
Fix minor deficiency in machine-sink.
Register uses that are MRI->isConstantPhysReg() should not inhibit sinking transformation.
Reviewed By: StephenTozer
Differential Revision: https://reviews.llvm.org/D111531
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#
ef2d0e0f |
| 10-Nov-2021 |
Kazu Hirata <kazu@google.com> |
[llvm] Use MachineBasicBlock::{successors,predecessors} (NFC)
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