Clean up.

llvm-svn: 31957

Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.

llvm-svn: 31947

setOperand should not zap the operand list or add implicit operands to an
instruction. Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.

This fixes PR1012 and CodeGen/

setOperand should not zap the operand list or add implicit operands to an
instruction. Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.

This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll

llvm-svn: 31876

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Minor updates.

llvm-svn: 31761

- Let MachineInstr ctors add implicit def and use operands. Other operands
will be inserted before these operands. If the opcode changes (by
setOpcode), the implicit operands are updated as well.

- Let MachineInstr ctors add implicit def and use operands. Other operands
will be inserted before these operands. If the opcode changes (by
setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
that move kill / dead info to MachineInstr's.

llvm-svn: 31711

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Add methods to add implicit def use operands to a MI.

llvm-svn: 31675

Add implicit def / use operands to MachineInstr.

llvm-svn: 31633

be more aggressive about matching identical instructions.

llvm-svn: 31179

implement MachineOperand::isIdenticalTo

llvm-svn: 31088

Only call isUse/isDef on register operands

llvm-svn: 30118

Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32

Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791

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Remove a bogus cast.

llvm-svn: 28492

Final pass of minor cleanups for MachineInstr

llvm-svn: 28110

Remove redundancy and a level of indirection when creating machine operands

llvm-svn: 28107

Remove and simplify some more machineinstr/machineoperand stuff.

llvm-svn: 28105

Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.

llvm-svn: 28104

Move some methods out of MachineInstr into MachineOperand

llvm-svn: 28102

There shalt be only one "immediate" operand type!

llvm-svn: 28099

Change "value" in MachineOperand to be a GlobalValue, as that is the only
thing that can be in it. Remove a dead method.

llvm-svn: 28098

Remove a bunch more dead V9 specific stuff

llvm-svn: 28094

Remove a bunch more SparcV9 specific stuff

llvm-svn: 28093

Remove some more V9-specific stuff.

llvm-svn: 28092

Remove some more unused stuff from MachineInstr that was leftover from V9.

llvm-svn: 28091

JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in th

JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947

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This field no longer exists

llvm-svn: 27899