Decode and pretty print inline asm operand descriptors.

The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so

Decode and pretty print inline asm operand descriptors.

The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901

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Handle debug info for i128 constants.

llvm-svn: 133821

Re-commit 131172 with fix. MachineInstr identity checks should check dead
markers. In some cases a register def is dead on one path, but not on
another.

This is passing Clang self-hosting.

llvm-svn

Re-commit 131172 with fix. MachineInstr identity checks should check dead
markers. In some cases a register def is dead on one path, but not on
another.

This is passing Clang self-hosting.

llvm-svn: 131214

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Remove an assertion to fix PR9872.

It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register.

Remove an assertion to fix PR9872.

It can happen that a live debug variable is the last use of a sub-register, and
the register allocator will pick a larger register class for the virtual
register. If the allocated register doesn't support the sub-register index,
just use %noreg for the debug variables instead of asserting.

In PR9872, a debug variable ends up in the sub_8bit_hi part of a GR32_ABCD
register. The register is split and one part is inflated to GR32 and assigned
%ESI because there are no more normal uses of sub_8bit_hi.

Since %ESI doesn't have that sub-register, substPhysReg asserted. Now it will
simply insert a %noreg instead, and the debug variable will be marked
unavailable in that range.

We don't currently have a way of saying: !"value" is in bits 8-15 of %ESI, I
don't know if DWARF even supports that.

llvm-svn: 131073

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Print out the 'nontemporal' info on a store.

llvm-svn: 130562

Ensure all defs referring to a virtual register are marked dead by addRegisterDead().

There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dea

Ensure all defs referring to a virtual register are marked dead by addRegisterDead().

There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

llvm-svn: 128888

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Add FrameSetup MI flags

llvm-svn: 127098

Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 1

Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

llvm-svn: 123155

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Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first vi

Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107

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Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnm

Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044

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DBG_VALUE does not have any side effects; it also makes no sense to mark it cheap as a copy.

llvm-svn: 123031

Unbreak build.

llvm-svn: 117155

Make CodeGen TBAA-aware.

llvm-svn: 116890

Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.

Pull an unsigned out of the Contents union such that it has the same size as two
pointers and no padding.

Arrange members such that the Co

Shrink MachineOperand from 40 to 32 bytes on 64-bit hosts.

Pull an unsigned out of the Contents union such that it has the same size as two
pointers and no padding.

Arrange members such that the Contents union and all pointers can be 8-byte
aligned without padding.

This speeds up code generation by 0.8% on a 64-bit host. 32-bit hosts should be
unaffected.

llvm-svn: 116857

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convert a couple more places to use the new getStore()

llvm-svn: 114463

add some accessors

llvm-svn: 114409

it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSour

it's more elegant to put the "getConstantPool" and
"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406

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add some helpful accessors.

llvm-svn: 114400

start pushing MachinePointerInfo out through the MachineMemOperand interface
to the MachineFunction construction methods.

llvm-svn: 114390

refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies

refactor the Value*/offset pair from MachineMemOperand out to a new
MachinePointerInfo struct, no functionality change.

This also adds an assert to MachineMemOperand::MachineMemOperand
that verifies that the Value* is either null or is an IR pointer type.

llvm-svn: 114389

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Prefix `next' iterator operation with `llvm::'.

Fixes potential ambiguity problems on VS 2010.

Patch by nobled!

llvm-svn: 110029

Print out the regclass of any virtual registers used by a machine instruction.

llvm-svn: 109608

Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.

llvm-svn: 107602

Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Ap

Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not. gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks. There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it. PR 5125. Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now. I'm not making it any
worse. If anyone is inspired I think you can find all
the right places from this patch.

llvm-svn: 107506

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Print InlinedAt location.

llvm-svn: 107208