[RegScavenger] Simplify state tracking for backwards scavenging (#71202)

Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the sta

[RegScavenger] Simplify state tracking for backwards scavenging (#71202)

Track the live register state immediately before, instead of after,
MBBI. This makes it simple to track the state at the start or end of a
basic block without a separate (and poorly named) Tracking flag.

This changes the API of the backward(MachineBasicBlock::iterator I)
method, which now recedes to the state just before, instead of just
after, *I. Some clients are simplified by this change.

There is one small functional change shown in the lit tests where
multiple spilled registers all need to be reloaded before the same
instruction. The reloads will now be inserted in the opposite order.
This should not affect correctness.

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[RegScavenger] Remove support for forwards register scavenging

Differential Revision: https://reviews.llvm.org/D156987

[RegScavenger] Remove scavengeRegister

All users have been converted to scavengeRegisterBackwards.

Differential Revision: https://reviews.llvm.org/D152425

[RegScavenger] Change scavengeRegister to pick registers in allocation order

This matches what scavengeRegisterBackwards does.

This is in preparation for converting most uses of scavengeRegister to

[RegScavenger] Change scavengeRegister to pick registers in allocation order

This matches what scavengeRegisterBackwards does.

This is in preparation for converting most uses of scavengeRegister to
scavengeRegisterBackwards, to reduce test case churn when that lands and
to help with bisection if anything goes wrong.

Differential Revision: https://reviews.llvm.org/D150792

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[RegScavenger] Simplify forward(MachineBasicBlock::iterator). NFC.

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differentia

Fix uninitialized pointer members in CodeGen

This change initializes the members TSI, LI, DT, PSI, and ORE pointer feilds of the SelectOptimize class to nullptr.

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D148303

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[CodeGen] Use range-based for loops (NFC)

RegScavenger: Add function to externally reserve a scavenging index

AMDGPU separately tracks the frame index we use for the emergency
spill slot. In the case where we need to spill SGPRs to memory,

RegScavenger: Add function to externally reserve a scavenging index

AMDGPU separately tracks the frame index we use for the emergency
spill slot. In the case where we need to spill SGPRs to memory, we
manually handle the save and restore. In other cases, the scavenger
handles the spills normally.

In a future change, I will need to add a second scavenging index in
order to free a second register in case we are spilling to a large
offset and also have to avoid clobbering a condition register
(SCC). In the intersection of these two cases, we will end up
recursively calling eliminateFrameIndex. We need to report to the
scavenger that the first scavenging frame index is unavailable, and
that the register is already used to avoid double spilling to the
scavenging slot (and avoid clobbering the previously evicted register,
and getting the same register for both scavenge calls).

This is really ugly but I don't see a better way without requiring
targets to be far more aware of how the scavenger iterator is
advanced.

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[CodeGen] Remove unused declaration setLiveInsUsed (NFC)

The corresponding definition was removed on Jan 20, 2017 in commit
710a4c1f3ddba3aa9313c72c43f9619afbc3e259.

[NFC][regalloc] Use MCRegister appropriately

Differential Revision: https://reviews.llvm.org/D90506

[RegisterScavenging] Delete dead function unprocess().

RegScavenger: Use Register

llvm-svn: 369794

RegisterScavenger: Allow fail without spill

AMDGPU wants to use this in some contexts where
the spilling is either impossible, or a worse alternative
to doing something else.

llvm-svn: 354816

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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[CodeGen] Fix inconsistent declaration parameter name

llvm-svn: 337200

RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse
to place spills as the very first instruciton of a basic block and thus
artific

RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse
to place spills as the very first instruciton of a basic block and thus
artifically increase pressure (test in
test/CodeGen/PowerPC/scavenging.mir:spill_at_begin)

This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/backward(). The benefit of the backward mode is
that it is not affected by incomplete kill flags.

This patch also changes
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register
scavenger in backwards mode.

Differential Revision: http://reviews.llvm.org/D21885

llvm-svn: 305625

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Revert "RegScavenging: Add scavengeRegisterBackwards()"

Revert because of reports of some PPC input starting to spill when it
was predicted that it wouldn't and no spillslot was reserved.

This reve

Revert "RegScavenging: Add scavengeRegisterBackwards()"

Revert because of reports of some PPC input starting to spill when it
was predicted that it wouldn't and no spillslot was reserved.

This reverts commit r305516.

llvm-svn: 305566

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RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64
problems reported in the stage2 build last time, which I cannot
reproduce right now

RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64
problems reported in the stage2 build last time, which I cannot
reproduce right now.

This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/backward(). The benefit of the backward mode is
that it is not affected by incomplete kill flags.

This patch also changes
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register
scavenger in backwards mode.

Differential Revision: http://reviews.llvm.org/D21885

llvm-svn: 305516

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RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFC

These parts do not depend on any PrologEpilogInserter logic and
therefore better fits RegisterScaveging.cpp.

llvm-svn:

RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFC

These parts do not depend on any PrologEpilogInserter logic and
therefore better fits RegisterScaveging.cpp.

llvm-svn: 304596

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[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

llvm-svn: 295773

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liven

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liveness tracking parts of the
RegisterScavenger factored out into an own class.

This was proposed in http://llvm.org/PR27609

Differential Revision: http://reviews.llvm.org/D21916

llvm-svn: 292542

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Extract LaneBitmask into a separate type

Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initializa

Extract LaneBitmask into a separate type

Specifically avoid implicit conversions from/to integral types to
avoid potential errors when changing the underlying type. For example,
a typical initialization of a "full" mask was "LaneMask = ~0u", which
would result in a value of 0x00000000FFFFFFFF if the type was extended
to uint64_t.

Differential Revision: https://reviews.llvm.org/D27454

llvm-svn: 289820

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Revert "RegScavenging: Add scavengeRegisterBackwards()"

The ppc64 multistage bot fails on this.

This reverts commit r279124.

Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because

Revert "RegScavenging: Add scavengeRegisterBackwards()"

The ppc64 multistage bot fails on this.

This reverts commit r279124.

Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change
This reverts commit r279171.

llvm-svn: 279199

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CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liven

CodeGen: Add/Factor out LiveRegUnits class; NFCI

This is a set of register units intended to track register liveness, it
is similar in spirit to LivePhysRegs.
You can also think of this as the liveness tracking parts of the
RegisterScavenger factored out into an own class.

This was proposed in http://llvm.org/PR27609

Differential Revision: http://reviews.llvm.org/D21916

llvm-svn: 279171

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RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044 with off-by-1 instruction fix for the reload placement.

This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/b

RegScavenging: Add scavengeRegisterBackwards()

Re-apply r276044 with off-by-1 instruction fix for the reload placement.

This is a variant of scavengeRegister() that works for
enterBasicBlockEnd()/backward(). The benefit of the backward mode is
that it is not affected by incomplete kill flags.

This patch also changes
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register
scavenger in backwards mode.

Differential Revision: http://reviews.llvm.org/D21885

llvm-svn: 279124

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