[clang-format] Handle Verilog assign statements

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D146402

[clang-format] More work on space around operators in Verilog

before:
```
(opcode *>o1) = 6.1;
a inside{b, c};
x = { >> {j}};
```

after:
```
(opcode *> o1) = 6.1;
a inside {b, c};
x = {>>{j}};
```

[clang-format] More work on space around operators in Verilog

before:
```
(opcode *>o1) = 6.1;
a inside{b, c};
x = { >> {j}};
```

after:
```
(opcode *> o1) = 6.1;
a inside {b, c};
x = {>>{j}};
```

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D146403

show more ...

[clang-format] Fix non-case colons in Verilog case lines

Back in D128714, we should have replaced the old rule about colons when
we added the new one. Because we didn't, all colons got mistaken as

[clang-format] Fix non-case colons in Verilog case lines

Back in D128714, we should have replaced the old rule about colons when
we added the new one. Because we didn't, all colons got mistaken as
case colons as long as the line began with `case` or `default`. Now we
remove the rule that we forgot to remove.

Reviewed By: MyDeveloperDay, rymiel

Differential Revision: https://reviews.llvm.org/D145888

show more ...

[clang-format] Recognize Verilog always blocks

The small `Coverage` test was added because we added the space rule
about 2 at signs along with the rule about only 1 of it. We have not
fully covered

[clang-format] Recognize Verilog always blocks

The small `Coverage` test was added because we added the space rule
about 2 at signs along with the rule about only 1 of it. We have not
fully covered covergroup yet.

Reviewed By: MyDeveloperDay, owenpan

Differential Revision: https://reviews.llvm.org/D145794

show more ...

[clang-format] Put ports on separate lines in Verilog module headers

New:
```
module mh1
(input var int in1,
input var in2, in3,
output tagged_st out);
endmodule
```

Old:
```
module m

[clang-format] Put ports on separate lines in Verilog module headers

New:
```
module mh1
(input var int in1,
input var in2, in3,
output tagged_st out);
endmodule
```

Old:
```
module mh1
(input var int in1, input var in2, in3, output tagged_st out);
endmodule
```

`getNextNonComment` was modified to return a non-const pointer because
we needed to use it that way in `verilogGroupDecl`.

The comment on line 2626 was a typo. We corrected it while modifying
the function.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D143825

show more ...

[clang-format] Recognize Verilog non-blocking assignment

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D142891

[clang-format] Handle Verilog attributes

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D128709

[clang-format] Handle Verilog case statements

These statements are like switch statements in C, but without the 'case'
keyword in labels.

How labels are parsed. In UnwrappedLineParser, the program

[clang-format] Handle Verilog case statements

These statements are like switch statements in C, but without the 'case'
keyword in labels.

How labels are parsed. In UnwrappedLineParser, the program tries to
parse a statement every time it sees a colon. In TokenAnnotator, a
colon that isn't part of an expression is annotated as a label.

The token type `TT_GotoLabelColon` is added. We did not include Verilog
in the name because we thought we would eventually have to fix the
problem that case labels in C can't contain ternary conditional
expressions and we would use that token type.

The style is like below. Labels are on separate lines and indented by
default. The linked style guide also has examples where labels and the
corresponding statements are on the same lines. They are not supported
for now.

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md

```
case (state_q)
StIdle:
state_d = StA;
StA: begin
state_d = StB;
end
endcase
```

Differential Revision: https://reviews.llvm.org/D128714

show more ...

[clang-format] Handle Verilog user-defined primitives

Differential Revision: https://reviews.llvm.org/D128713

[clang-format] Handle Verilog modules

Now things inside hierarchies like modules and interfaces are
indented. When the module header spans multiple lines, all except the
first line are indented as

[clang-format] Handle Verilog modules

Now things inside hierarchies like modules and interfaces are
indented. When the module header spans multiple lines, all except the
first line are indented as continuations. We added the property
`IsContinuation` to mark lines that should be indented this way.

In order that the colons inside square brackets don't get labeled as
`TT_ObjCMethodExpr`, we added a check to only use this type when the
language is not Verilog.

Differential Revision: https://reviews.llvm.org/D128712

show more ...

[clang-format] Handle Verilog blocks

Now stuff inside begin-end blocks get indented.

Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with

[clang-format] Handle Verilog blocks

Now stuff inside begin-end blocks get indented.

Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with if statements.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D128711

show more ...

[clang-format] Handle Verilog numbers and operators

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D126845

[clang-format] Handle Verilog preprocessor directives

Verilog uses the backtick instead of the hash. In this revision
backticks are lexed manually and then get labeled as hashes so the logic
for ha

[clang-format] Handle Verilog preprocessor directives

Verilog uses the backtick instead of the hash. In this revision
backticks are lexed manually and then get labeled as hashes so the logic
for handling C preprocessor stuff don't have to change. Hashes get
labeled as identifiers for Verilog-specific stuff like delays.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D124749

show more ...

[clang-format] Parse Verilog if statements

This patch mainly handles treating `begin` as block openers.

While and for statements will be handled in another patch.

Reviewed By: HazardyKnusperkeks

[clang-format] Parse Verilog if statements

This patch mainly handles treating `begin` as block openers.

While and for statements will be handled in another patch.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D123450

show more ...