[clang-format] Stop crashing on slightly off Verilog module headers (#116000)

This piece of code made the program crash.

```Verilog
function pkg::t get
(int t = 2,
int f = 2);
```

The way

[clang-format] Stop crashing on slightly off Verilog module headers (#116000)

This piece of code made the program crash.

```Verilog
function pkg::t get
(int t = 2,
int f = 2);
```

The way the code is supposed to be parsed is that UnwrappedLineParser
should identify the function header, and then TokenAnnotator should
recognize the result. But the code in UnwrappedLineParser would
mistakenly not recognize it due to the `::`. Then TokenAnnotator would
recognize the comma both as TT_VerilogInstancePortComma and
TT_VerilogTypeComma. The code for annotating the instance port comma
used `setFinalizedType`. The program would crash when it tried to set
it to another type.

The code in UnwrappedLineParser now recognizes the `::` token.

The are other cases in which TokenAnnotator would recognize the comma as
both of those types, for example if the `function` keyword is removed.
The type is now set using `setType` instead so that the program does not
crash. The developer no longer knows why he used `setFinalizedType`
back then.

show more ...

[clang-format] Stop crashing when formatting Verilog (#112043)

The part of the code for parsing Verilog module instantiations
dereferenced a pointer without checking for null pointer. The pointer

[clang-format] Stop crashing when formatting Verilog (#112043)

The part of the code for parsing Verilog module instantiations
dereferenced a pointer without checking for null pointer. The pointer
may be null if the input is not complete and a line starts with a comma.

show more ...

[clang-format] Handle Verilog delay control (#95703)

I made a mistake when I tried to make the code handle the backtick
character like the hash character. The code did not recognize the delay
contr

[clang-format] Handle Verilog delay control (#95703)

I made a mistake when I tried to make the code handle the backtick
character like the hash character. The code did not recognize the delay
control structure. It caused net names in the declaration to be aligned
to the type name instead of the first net name.

new

```Verilog
wire logic #0 mynet, //
mynet1;
```

old

```Verilog
wire logic #0 mynet, //
mynet1;
```

show more ...

[clang-format][NFC] Remove redundnat llvm::, clang::, etc.

[clang-format] Stop aligning the to continuation lines (#76378)

Some unwrapped lines are marked as continuations of the previous lines,
for example the ports in a Verilog module header. Previously,

[clang-format] Stop aligning the to continuation lines (#76378)

Some unwrapped lines are marked as continuations of the previous lines,
for example the ports in a Verilog module header. Previously, if the
first line following the ports line was changed, and git-clang-format
was run, the changed line would be indented by an extra continuation
indentation.

show more ...

[clang-format] Add space in Verilog tagged unions (#71354)

In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part

[clang-format] Add space in Verilog tagged unions (#71354)

In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part of a
dotted identifier or a struct literal, and the space would be omitted.

show more ...

[clang-format] Indent Verilog case statements with comments (#71353)

If a line contains a comment outside of (fake) parentheses, the part
following it is indented according to `CurrentState.Indent`

[clang-format] Indent Verilog case statements with comments (#71353)

If a line contains a comment outside of (fake) parentheses, the part
following it is indented according to `CurrentState.Indent`. A Verilog
case label and the statement that follows are broken with
mustBreakBefore. So the part that follows the case label needs some
special handling. Previously, that variable was left out. So the
indentation was wrong when there was a comment.

old:

```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//

//
result = //
10'b0111111111;
endcase
```

new:

```Verilog
case (data)
16'd0:
result = //
10'b0111111111;
endcase
case (data)
16'd0:
//

//
result = //
10'b0111111111;
endcase
```

show more ...

[clang-format] Add spaces around the Verilog implication operator (#71352)

The Verilog implication operator `->` is a binary operator meaning
either the left hand side is false or the right hand si

[clang-format] Add spaces around the Verilog implication operator (#71352)

The Verilog implication operator `->` is a binary operator meaning
either the left hand side is false or the right hand side is true.
Previously it was treated as the C++ struct member operator.

I didn't even know it existed when I added the operator formatting part.
And I didn't check all the tests for all the operators I added. That is
how the bad test got in.

show more ...

[clang-format][NFC] Remove more extraneous newlines in unit tests

Also removed a duplicate test case.

[clang-format] Don't split "DPI"/"DPI-C" in Verilog imports (#66951)

The spec doesn't allow splitting these strings and we're seeing compile
issues with splitting it.

String splitting was enable

[clang-format] Don't split "DPI"/"DPI-C" in Verilog imports (#66951)

The spec doesn't allow splitting these strings and we're seeing compile
issues with splitting it.

String splitting was enabled for Verilog in
https://reviews.llvm.org/D154093.

show more ...

[clang-format] Properly indent lines inside Verilog case structure (#65861)

When a statement following a case label had to be broken into multiple
lines, the continuation parts were not indented co

[clang-format] Properly indent lines inside Verilog case structure (#65861)

When a statement following a case label had to be broken into multiple
lines, the continuation parts were not indented correctly.

Old:

```Verilog
case (data)
16'd0:
result = // break here
10'b0111111111;
endcase
```

New:

```Verilog
case (data)
16'd0:
result = // break here
10'b0111111111;
endcase
```

Verilog case labels and the following statements are on the same
unwrapped line due to the difficulty of identifying them. So there was a
rule in `getNewLineColumn` to add a level of indentation to the part
following the case label. However, in case the line had to be broken
again, the code at the end of the function would see that the line was
already broken with the continuation part indented, so it would not
indent it more. Now `State.FirstIndent` is changed as well for the part
following the case label, so the logic for determining when to add a
continuation indentation works.

show more ...

[clang-format] Break long string literals in C#, etc.

Now strings that are too long for one line in C#, Java, JavaScript, and
Verilog get broken into several lines. C# and JavaScript interpolated
s

[clang-format] Break long string literals in C#, etc.

Now strings that are too long for one line in C#, Java, JavaScript, and
Verilog get broken into several lines. C# and JavaScript interpolated
strings are not broken.

A new subclass BreakableStringLiteralUsingOperators is used to handle
the logic for adding plus signs and commas. The updateAfterBroken
method was added because now parentheses or braces may be required after
the parentheses or commas are added. In order to decide whether the
added plus sign should be unindented in the BreakableToken object, the
logic for it is taken out into a separate function
shouldUnindentNextOperator.

The logic for finding the continuation indentation when the option
AlignAfterOpenBracket is set to DontAlign is not implemented yet. So in
that case the new line may have the wrong indentation, and the parts may
have the wrong length if the string needs to be broken more than once
because finding where to break the string depends on where the string
starts.

The preambles for the C# and Java unit tests are changed to the newer
style in order to allow the 3-argument verifyFormat macro. Some cases
are changed from verifyFormat to verifyImcompleteFormat because those
use incomplete code and the new verifyFormat function checks that the
code is complete.

The line in the doc was changed to being indented by 4 spaces, that is,
the default continuation indentation. It has always been the case. It
was probably a mistake that the doc showed 2 spaces previously.

This commit was fist committed as 16ccba51072b. The tests caused
assertion failures. Then it was reverted in 547bce36132a.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D154093

show more ...

Revert "[clang-format] Break long string literals in C#, etc."

This reverts commit 16ccba51072bbc5ff4c66f91f939163dc91e5d96.

This is failing across Linaro's bots e.g.:
https://lab.llvm.org/buildbot

Revert "[clang-format] Break long string literals in C#, etc."

This reverts commit 16ccba51072bbc5ff4c66f91f939163dc91e5d96.

This is failing across Linaro's bots e.g.:
https://lab.llvm.org/buildbot/#/builders/188/builds/34393

show more ...

[clang-format] Break long string literals in C#, etc.

Now strings that are too long for one line in C#, Java, JavaScript, and
Verilog get broken into several lines. C# and JavaScript interpolated
s

[clang-format] Break long string literals in C#, etc.

Now strings that are too long for one line in C#, Java, JavaScript, and
Verilog get broken into several lines. C# and JavaScript interpolated
strings are not broken.

A new subclass BreakableStringLiteralUsingOperators is used to handle
the logic for adding plus signs and commas. The updateAfterBroken
method was added because now parentheses or braces may be required after
the parentheses or commas are added. In order to decide whether the
added plus sign should be unindented in the BreakableToken object, the
logic for it is taken out into a separate function
shouldUnindentNextOperator.

The logic for finding the continuation indentation when the option
AlignAfterOpenBracket is set to DontAlign is not implemented yet. So in
that case the new line may have the wrong indentation, and the parts may
have the wrong length if the string needs to be broken more than once
because finding where to break the string depends on where the string
starts.

The preambles for the C# and Java unit tests are changed to the newer
style in order to allow the 3-argument verifyFormat macro. Some cases
are changed from verifyFormat to verifyImcompleteFormat because those
use incomplete code and the new verifyFormat function checks that the
code is complete.

The line in the doc was changed to being indented by 4 spaces, that is,
the default continuation indentation. It has always been the case. It
was probably a mistake that the doc showed 2 spaces previously.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D154093

show more ...

[clang-format] Add SpacesInParens with SpacesInParensOptions

This is a refactoring of:
- SpacesInConditionalStatement
- SpacesInCStyleCastParentheses
- SpaceInEmptyParentheses
- SpacesInParentheses

[clang-format] Add SpacesInParens with SpacesInParensOptions

This is a refactoring of:
- SpacesInConditionalStatement
- SpacesInCStyleCastParentheses
- SpaceInEmptyParentheses
- SpacesInParentheses

These are now options under the new Style Option: SpacesInParens. The
existing options are maintained for backward compatibility.

Within SpacesInParens, there are currently options for:
- Never
- Custom

The currently available options for Custom are:
- InConditionalStatements
- InCStyleCasts
- InEmptyParentheses
- Other

Setting InConditionalStatements and Other to true enables the same space
additions as SpacesInParentheses.

This refactoring does not add or remove any existing features, but it makes
it possible to more easily extend and maintain the addition of spaces within
parentheses.

Related to #55428.

Differential Revision: https://reviews.llvm.org/D155239

show more ...

[clang-format] Indent Verilog struct literal on new line

Before:
```
c = //
'{default: 0};
```

After:
```
c = //
'{default: 0};
```

If the line has to be broken, the continuation part should b

[clang-format] Indent Verilog struct literal on new line

Before:
```
c = //
'{default: 0};
```

After:
```
c = //
'{default: 0};
```

If the line has to be broken, the continuation part should be
indented. Before this fix, it was not the case if the continuation
part was a struct literal. The rule that caused the problem was added
in 783bac6b. It was intended for aligning the field labels in
ProtoBuf. The type `TT_DictLiteral` was only for colons back then, so
the program didn't have to check whether the token was a colon when it
was already type `TT_DictLiteral`. Now the type applies to more
things including the braces enclosing a dictionary literal. In
Verilog, struct literals start with a quote. The quote is regarded as
an identifier by the program. So the rule for aligning the fields in
ProtoBuf applied to this situation by mistake.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D152623

show more ...

[clang-format] Stop comment disrupting indentation of Verilog ports

Before:

```
module x
#( //
parameter x)
( //
input y);
endmodule
```

After:

```
module x
#(//

[clang-format] Stop comment disrupting indentation of Verilog ports

Before:

```
module x
#( //
parameter x)
( //
input y);
endmodule
```

After:

```
module x
#(//
parameter x)
(//
input y);
endmodule
```

If the first line in a port or parameter list is not a comment, the
following lines will be aligned to the first line as intended:

```
module x
#(parameter x1,
parameter x2)
(input y,
input y2);
endmodule
```

Previously, the indentation would be changed to an extra continuation
indentation relative to the start of the parenthesis or the hash if
the first token inside the parentheses was a comment. It is a feature
introduced in ddaa9be97839. The feature enabled one to insert a `//`
comment right after an opening parentheses to put the function
arguments on a new line with a small indentation regardless of how
long the function name is, like this:

```
someFunction(anotherFunction( // Force break.
parameter));
```

People are unlikely to use this feature in a Verilog port list because
the formatter already puts the port list on its own lines. A comment
at the start of a port list is probably a comment for the port on the
next line.

We also removed the space before the comment so that its indentation
would be same as that for a line comment anywhere else in the port
list.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149562

show more ...

[clang-format] Don't indent Verilog `begin` keyword on its own line

When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.

Reviewed By: HazardyKnusperke

[clang-format] Don't indent Verilog `begin` keyword on its own line

When the line is too long and the `begin` keyword wraps to the next
line, it shouldn't be indented.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149657

show more ...

[clang-format] Recognize Verilog edge identifiers

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma. The events can be
separated wit

[clang-format] Recognize Verilog edge identifiers

Previously the event expression would be misidentified as a port list.
A line break would be added after the comma. The events can be
separated with either a comma or the `or` keyword, and a line break
would not be inserted if the `or` keyword was used. We changed the
behavior of the comma to match the `or` keyword.

Before:
```
always @(posedge x,
posedge y)
x <= x;
always @(posedge x or posedge y)
x <= x;
```

After:
```
always @(posedge x, posedge y)
x <= x;
always @(posedge x or posedge y)
x <= x;
```

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149561

show more ...

[clang-format] Recognize Verilog type dimension in module header

We had the function `verilogGroupDecl` for that. However, the type
name would be incorrectly annotated in `isStartOfName` when it wa

[clang-format] Recognize Verilog type dimension in module header

We had the function `verilogGroupDecl` for that. However, the type
name would be incorrectly annotated in `isStartOfName` when it was not
a C++ keyword and followed another identifier.

Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D149352

show more ...

[clang-format] Handle Verilog assertions and loops

Assert statements in Verilog can optionally have an else part. We
handle them like for `if` statements, except that an `if` statement in
the else

[clang-format] Handle Verilog assertions and loops

Assert statements in Verilog can optionally have an else part. We
handle them like for `if` statements, except that an `if` statement in
the else part of an `assert` statement doesn't get merged with the
`else` keyword. Like this:

assert (x)
$info();
else
if (y)
$info();
else if (z)
$info();
else
$info();

`foreach` and `repeat` are now handled like for or while loops.

We used the type `TT_ConditionLParen` to mark the condition part so
they are handled in the same way as the condition part of an `if`
statement. When the code being formatted is not in Verilog, it is
only set for `if` statements, not loops. It's because loop conditions
are currently handled slightly differently, and existing behavior is
not supposed to change. We formatted all files ending in `.cpp` and
`.h` in the repository with and without this change. It showed that
setting the type for `if` statements doesn't change existing behavior.

And we noticed that we forgot to make the program print the list of
tokens when the number is not correct in `TokenAnnotatorTest`. It's
fixed now.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D147895

show more ...

[clang-format] Add option for having one port per line in Verilog

We added the option `VerilogBreakBetweenInstancePorts` to put ports on
separate lines in module instantiations. We made it default

[clang-format] Add option for having one port per line in Verilog

We added the option `VerilogBreakBetweenInstancePorts` to put ports on
separate lines in module instantiations. We made it default to true
because style guides mostly recommend it that way for example:

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#module-instantiation

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D147327

show more ...

[clang-format] Handle Verilog struct literals

Previously `isVerilogIdentifier` was mistaking the apostrophe used in
struct literals as an identifier. It is fixed.

Reviewed By: HazardyKnusperkeks,

[clang-format] Handle Verilog struct literals

Previously `isVerilogIdentifier` was mistaking the apostrophe used in
struct literals as an identifier. It is fixed.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D147329

show more ...

[clang-format] Handle enum in Verilog

Verilog has enum just like C.

Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D147328

[clang-format] Don't squash Verilog escaped identifiers

An escaped identifier always needs a space following it so the parser
can tell it apart from the next token.

The unit tests are changed to us

[clang-format] Don't squash Verilog escaped identifiers

An escaped identifier always needs a space following it so the parser
can tell it apart from the next token.

The unit tests are changed to use `FormatTestBase.h` because we need the
2-argument version of `verifyFormat`. We also added the `messUp`
virtual function because Verilog needs a different version of it.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D146401

show more ...