[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new pr

[SystemZ] Add support for new cpu architecture - arch15

This patch adds support for the next-generation arch15
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch15 as host processor.
- Assembler/disassembler support for new instructions.
- Exploitation of new instructions for code generation.
- New vector (signed|unsigned|bool) __int128 data types.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining __VEC__ == 10305.

Note: No currently available Z system supports the arch15
architecture. Once new systems become available, the
official system name will be added as supported -march name.

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[X86] Add missing feature USERMSR to DiamondRapids (#120061)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Reland "[X86] Support -march=diamondrapids (#113881)" (#116564)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

Revert "[X86] Support -march=diamondrapids (#113881)" (#116563)

This reverts commit 826b845c9e97448395431be3e4e5da585bd98c5e.

[X86] Support -march=diamondrapids (#113881)

Ref.: https://cdrdv2.intel.com/v1/dl/getContent/671368

[Driver][Sparc] Default to -mcpu=v9 for 32-bit Linux/sparc64 (#109278)

While working on supporting PR #109101 on Linux/sparc64, I was reminded
that `clang -m32` still defaults to generating V8 code

[Driver][Sparc] Default to -mcpu=v9 for 32-bit Linux/sparc64 (#109278)

While working on supporting PR #109101 on Linux/sparc64, I was reminded
that `clang -m32` still defaults to generating V8 code, although the
64-bit kernel requires a V9 CPU.

This patch corrects that.

Tested on `sparc64-unknown-linux-gnu`, `x86_64-pc-linux-gnu`,
`sparcv9-sun-solaris2.11`, and `amd64-pc-solaris2.11`.

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[X86] AMD Zen 5 Initial enablement (#107964)

This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.

[z/OS] Set the default arch for z/OS to be arch10 (#89854)

The default arch level on z/OS is arch10. Update the code so z/OS has
arch10 without changing the default for zLinux.

Remove support for 3DNow!, both intrinsics and builtins. (#96246)

This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family

Remove support for 3DNow!, both intrinsics and builtins. (#96246)

This set of instructions was only supported by AMD chips starting in
the K6-2 (introduced 1998), and before the "Bulldozer" family
(2011). They were never much used, as they were effectively superseded
by the more-widely-implemented SSE (first implemented on the AMD side
in Athlon XP in 2001).

This is being done as a predecessor towards general removal of MMX
register usage. Since there is almost no usage of the 3DNow!
intrinsics, and no modern hardware even implements them, simple
removal seems like the best option.

(Clang half originally uploaded in https://reviews.llvm.org/D94213)

Works towards issue #41665 and issue #98272.

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Reland "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93136)

This reverts commit aa4069ea96e5eb62bc8c7895b9d920f129611b3a.

Revert "[X86] Remove knl/knm specific ISAs supports (#92883)" (#93123)

This reverts commit 282d2ab58f56c89510f810a43d4569824a90c538.

[X86] Remove knl/knm specific ISAs supports (#92883)

Cont. patch after https://github.com/llvm/llvm-project/pull/75580

[NVPTX] Allow compiling LLVM-IR without `-march` set (#79873)

Summary:
The NVPTX tools require an architecture to be used, however if we are
creating generic LLVM-IR we should be able to leave it un

[NVPTX] Allow compiling LLVM-IR without `-march` set (#79873)

Summary:
The NVPTX tools require an architecture to be used, however if we are
creating generic LLVM-IR we should be able to leave it unspecified. This
will result in the `target-cpu` attributes not being set on the
functions so it can be changed when linked into code. This allows the
standalone `--target=nvptx64-nvidia-cuda` toolchain to create LLVM-IR
simmilar to how CUDA's deviceRTL looks from C/C++

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[Clang] Fix test failing on systems without ROCm installed

Summary:
Forgot to specify `-nogpulib` which makes this test look for ROCm.

[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#80035)

Summary:
Currently, the AMDGPU toolchain accepts not passing `-mcpu` as a means
to create a sort of "generic" IR. The resulti

[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#80035)

Summary:
Currently, the AMDGPU toolchain accepts not passing `-mcpu` as a means
to create a sort of "generic" IR. The resulting IR will not contain any
target dependent attributes and can then be inserted into another
program via `-mlink-builtin-bitcode` to inherit its attributes.

However, there are a handful of macros that can leak incorrect
information when compiling for an unspecified architecture. Currently,
things like the wavefront size will default to 64, which is actually
variable. We should not expose these macros unless it is known.

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Revert "[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)"

This reverts commit c9a6e993f7b349405b6c8f9244cd9cf0f56a6a81.

This breaks HIP code that incorrectly depended on GPU

Revert "[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)"

This reverts commit c9a6e993f7b349405b6c8f9244cd9cf0f56a6a81.

This breaks HIP code that incorrectly depended on GPU-specific macros to
be set. The code is totally wrong as using `__WAVEFRTONSIZE__` on the
host is absolutely meaningless, but it seems this entire corner of the
toolchain is fundmentally broken. Reverting for now to avoid breakages.

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[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)

Summary:
Currently, the AMDGPU toolchain accepts not passing `-mcpu` as a means
to create a sort of "generic" IR. The resulti

[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)

Summary:
Currently, the AMDGPU toolchain accepts not passing `-mcpu` as a means
to create a sort of "generic" IR. The resulting IR will not contain any
target dependent attributes and can then be inserted into another
program via `-mlink-builtin-bitcode` to inherit its attributes.

However, there are a handful of macros that can leak incorrect
information when compiling for an unspecified architecture. Currently,
things like the wavefront size will default to 64, which is actually
variable. We should not expose these macros unless it is known.

show more ...

[X86] Remove RAO-INT from Grandridge (#76420)

According to latest spec:
https://cdrdv2.intel.com/v1/dl/getContent/671368

[X86] Add a EVEX256 macro to match with GCC and MSVC (#71317)

[X86] Support -march=pantherlake,clearwaterforest (#69277)

[X86][NFC]Update test cases after D159250 (#68517)

[Driver] Remove remnant myriad pieces after Myriad.cpp removal

after D104279 and D158706.

[X86] Support -march=gracemont

gracemont has some different tuning features from alderlake.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D158046

[X86] Support -march=arrowlake,arrowlake-s,lunarlake

Reviewed By: pengfei

Differential Revision: https://reviews.llvm.org/D156239

[X86] Support -march=graniterapids-d and update -march=graniterapids

Reviewed By: pengfei, RKSimon, skan

Differential Revision: https://reviews.llvm.org/D155798