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Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6 |
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c5de4dd1 |
| 05-May-2024 |
Fangrui Song <i@maskray.me> |
[test] %clang_cc1 -emit-llvm: remove redundant -S
And replace -emit-llvm -o - with -emit-llvm-only
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Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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eae26b66 |
| 04-Jan-2023 |
Paul Walker <paul.walker@arm.com> |
[IRBuilder] Use canonical i64 type for insertelement index used by vector splats.
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as a
[IRBuilder] Use canonical i64 type for insertelement index used by vector splats.
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as an integer so we may as well use the prefered form from creation.
NOTE: All test changes are mechanical with nothing else expected beyond a change of index type from i32 to i64.
Differential Revision: https://reviews.llvm.org/D140983
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5 |
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5f9a8268 |
| 06-Nov-2022 |
Bjorn Pettersson <bjorn.a.pettersson@ericsson.com> |
[clang][test] Use opt -passes=<name> instead of opt -name
Updated the RUN line in several test cases to use the new PM syntax opt -passes=<pipeline> instead of the deprecated syntax opt -pass1 -
[clang][test] Use opt -passes=<name> instead of opt -name
Updated the RUN line in several test cases to use the new PM syntax opt -passes=<pipeline> instead of the deprecated syntax opt -pass1 -pass2
This was not a complete cleanup in clang/test. But just a swipe using some simple search-and-replace. Mainly for RUN lines involving -mem2reg, -instnamer and -early-cse.
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Revision tags: llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2 |
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123064dc |
| 29-Sep-2022 |
David Green <david.green@arm.com> |
[Clang][Arm] Convert -fallow-half-arguments-and-returns to a target option. NFC
This cc1 option -fallow-half-arguments-and-returns allows __fp16 to be passed by argument and returned, without giving
[Clang][Arm] Convert -fallow-half-arguments-and-returns to a target option. NFC
This cc1 option -fallow-half-arguments-and-returns allows __fp16 to be passed by argument and returned, without giving an error. It is currently always enabled for Arm and AArch64, by forcing the option in the driver. This means any cc1 tests (especially those needing arm_neon.h) need to specify the option too, to prevent the error from being emitted.
This changes it to a target option instead, set to true for Arm and AArch64. This allows the option to be removed. Previously it was implied by -fnative_half_arguments_and_returns, which is set for certain languages like open_cl, renderscript and hlsl, so that option now too controls the errors. There were are few other non-arm uses of -fallow-half-arguments-and-returns but I believe they were unnecessary. The strictfp_builtins.c tests were converted from __fp16 to _Float16 to avoid the issues.
Differential Revision: https://reviews.llvm.org/D133885
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Revision tags: llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1 |
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d96161a1 |
| 13-Nov-2021 |
David Green <david.green@arm.com> |
[ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4b125e5561925aa added REQUIRES lines to a lot of Arm and AArch64 test, but added them to the very beginning, before the existi
[ARM/AArch64] Move REQUIRES after update_cc_test_checks line. NFC
c17d9b4b125e5561925aa added REQUIRES lines to a lot of Arm and AArch64 test, but added them to the very beginning, before the existing update_cc_test_checks lines. This just moves them later so as to not mess up the existing ordering when the checks are regenerated.
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c17d9b4b |
| 09-Nov-2021 |
Saleem Abdulrasool <compnerd@compnerd.org> |
headers: optionalise some generated resource headers
This splits out the generated headers and conditonalises them upon the target being enabled.
The motivation here is that the RISCV header alone
headers: optionalise some generated resource headers
This splits out the generated headers and conditonalises them upon the target being enabled.
The motivation here is that the RISCV header alone added 10MB to the resource directory, which was previously at 10MB, increasing the build size and time. This header is contributing ~50% of the size of the resource headers (~10MB).
The ARM generated headers are contributing about ~10% or 1MB.
This could be extended further adding only the static resource headers for the targets that the LLVM build supports.
The changes to the tests for ARM mirror what the RISCV target already did and rnk identified as a possible issue.
Testing: cmake -G Ninja -D LLVM_TARGETS_TO_BUILD=X86 -D LLVM_ENABLE_PROJECTS="clang;lld" ../clang ninja check-clang
Differential Revision: https://reviews.llvm.org/D112890 Reviewed By: craig.topper
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1 |
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278aa65c |
| 24-Dec-2020 |
Juneyoung Lee <aqjune@gmail.com> |
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder
This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder.
Reviewed By: n
[IR] Let IRBuilder's CreateVectorSplat/CreateShuffleVector use poison as placeholder
This patch updates IRBuilder to create insertelement/shufflevector using poison as a placeholder.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D93793
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Revision tags: llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1 |
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eecba950 |
| 22-Apr-2020 |
David Green <david.green@arm.com> |
[ARM] Replace arm vendor with none. NFC
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Revision tags: llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3 |
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489f62e8 |
| 17-Feb-2020 |
Mikhail Maltsev <mikhail.maltsev@arm.com> |
[ARM,MVE] Add vector-scalar intrinsics
Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdm
[ARM,MVE] Add vector-scalar intrinsics
Summary: This patch adds vector-scalar variants to the following families of MVE intrinsics: * vaddq * vsubq * vmulq * vqaddq * vqsubq * vhaddq * vhsubq * vqdmulhq * vqrdmulhq
The vector-scalar variants perform a splat operation on the scalar operand and then perform the same operations as their vector-vector counterparts. Code generation is done accordingly (using LLVM IR 'insert' and 'shuffle' operations which are later converted into an ARMvdup SDNode).
Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard
Reviewed By: dmgreen
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74620
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Revision tags: llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init |
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a2cd4600 |
| 13-Dec-2019 |
Mark Murray <mark.murray@arm.com> |
[ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed numbers.
Fix broken tests. I can't yet explain how they worked locally pre-commit.
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Revision tags: llvmorg-9.0.1, llvmorg-9.0.1-rc3 |
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fc3417cb |
| 06-Dec-2019 |
Mark Murray <mark.murray@arm.com> |
[ARM][MVE][Intrinsics] Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ, VQRDMULHQ intrinsics.
Summary: Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ, VQRDMULHQ intrinsics and unit test
[ARM][MVE][Intrinsics] Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ, VQRDMULHQ intrinsics.
Summary: Add VQADDQ, VHADDQ, VRHADDQ, VQSUBQ, VHSUBQ, VQDMULHQ, VQRDMULHQ intrinsics and unit tests.
Reviewers: simon_tatham, ostannard, dmgreen, miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D71198
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