Revision tags: llvmorg-21-init |
|
#
7e22180c |
| 28-Jan-2025 |
Chandler Carruth <chandlerc@gmail.com> |
[StrTable] Mechanically convert Hexagon builtins to use TableGen (#123460)
This switches them to use the common builtin TableGen emission.
The fancy feature string preprocessor tricks are replace
[StrTable] Mechanically convert Hexagon builtins to use TableGen (#123460)
This switches them to use the common builtin TableGen emission.
The fancy feature string preprocessor tricks are replaced with a fairly
direct translation into TableGen.
All of the actual definitions were created using a quite hack-y Python
script that was never intended to be productionized. It preserves the
order, spacing, and even comments from the original files. For
posterity, the script used is here:
https://gist.github.com/chandlerc/f53c7d735e33eecf388529bd9a6010df
The original `.def` file appears to be generated by some out-of-tree
`iset.py` script, which because it is out of tree I couldn't update. It
should be very straightforward though to update it to generate a similar
structure as was used to produce the `.td` file.
In addition to helping move towards TableGen for all of the builtins,
these builtins in particular can be *much* more efficiently handled
using TableGen when we start emitting string tables for them because it
allows de-duplicating all of the feature strings.
The commit sha parent at the time the PR was made is
7253c6fde498c4c9470b681df47d46e6930d6a02 and at that commit, the
resulting TableGen file produces a `.inc` file that only differs in
whitespace and the order of the builtins defined.
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|
Revision tags: llvmorg-19.1.7 |
|
#
c2b89fc9 |
| 23-Dec-2024 |
Ikhlas Ajbar <iajbar@quicinc.com> |
[Hexagon] Add V79 support to compiler and assembler (#120983)
This patch introduces support for the Hexagon V79 architecture. It
includes instruction formats, definitions, encodings, scheduling
cl
[Hexagon] Add V79 support to compiler and assembler (#120983)
This patch introduces support for the Hexagon V79 architecture. It
includes instruction formats, definitions, encodings, scheduling
classes, and builtins/intrinsics. It also adds missing Hexagon v73
builtins to clang.
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|
#
8b37c1c7 |
| 20-Dec-2024 |
Ikhlas Ajbar <iajbar@quicinc.com> |
[Hexagon] Add V75 support to compiler and assembler (#120773)
This patch introduces support for the Hexagon V75 architecture. It
includes instruction formats, definitions, encodings, scheduling
cl
[Hexagon] Add V75 support to compiler and assembler (#120773)
This patch introduces support for the Hexagon V75 architecture. It
includes instruction formats, definitions, encodings, scheduling
classes, and builtins/intrinsics.
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|
Revision tags: llvmorg-19.1.6 |
|
#
ca79ff07 |
| 14-Dec-2024 |
Chandler Carruth <chandlerc@gmail.com> |
Revert "Switch builtin strings to use string tables" (#119638)
Reverts llvm/llvm-project#118734
There are currently some specific versions of MSVC that are miscompiling
this code (we think). We
Revert "Switch builtin strings to use string tables" (#119638)
Reverts llvm/llvm-project#118734
There are currently some specific versions of MSVC that are miscompiling
this code (we think). We don't know why as all the other build bots and
at least some folks' local Windows builds work fine.
This is a candidate revert to help the relevant folks catch their
builders up and have time to debug the issue. However, the expectation
is to roll forward at some point with a workaround if at all possible.
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|
#
be2df95e |
| 09-Dec-2024 |
Chandler Carruth <chandlerc@gmail.com> |
Switch builtin strings to use string tables (#118734)
The Clang binary (and any binary linking Clang as a library), when built
using PIE, ends up with a pretty shocking number of dynamic relocation
Switch builtin strings to use string tables (#118734)
The Clang binary (and any binary linking Clang as a library), when built
using PIE, ends up with a pretty shocking number of dynamic relocations
to apply to the executable image: roughly 400k.
Each of these takes up binary space in the executable, and perhaps most
interestingly takes start-up time to apply the relocations.
The largest pattern I identified were the strings used to describe
target builtins. The addresses of these string literals were stored into
huge arrays, each one requiring a dynamic relocation. The way to avoid
this is to design the target builtins to use a single large table of
strings and offsets within the table for the individual strings. This
switches the builtin management to such a scheme.
This saves over 100k dynamic relocations by my measurement, an over 25%
reduction. Just looking at byte size improvements, using the `bloaty`
tool to compare a newly built `clang` binary to an old one:
```
FILE SIZE VM SIZE
-------------- --------------
+1.4% +653Ki +1.4% +653Ki .rodata
+0.0% +960 +0.0% +960 .text
+0.0% +197 +0.0% +197 .dynstr
+0.0% +184 +0.0% +184 .eh_frame
+0.0% +96 +0.0% +96 .dynsym
+0.0% +40 +0.0% +40 .eh_frame_hdr
+114% +32 [ = ] 0 [Unmapped]
+0.0% +20 +0.0% +20 .gnu.hash
+0.0% +8 +0.0% +8 .gnu.version
+0.9% +7 +0.9% +7 [LOAD #2 [R]]
[ = ] 0 -75.4% -3.00Ki .relro_padding
-16.1% -802Ki -16.1% -802Ki .data.rel.ro
-27.3% -2.52Mi -27.3% -2.52Mi .rela.dyn
-1.6% -2.66Mi -1.6% -2.66Mi TOTAL
```
We get a 16% reduction in the `.data.rel.ro` section, and nearly 30%
reduction in `.rela.dyn` where those reloctaions are stored.
This is also visible in my benchmarking of binary start-up overhead at
least:
```
Benchmark 1: ./old_clang --version
Time (mean ± σ): 17.6 ms ± 1.5 ms [User: 4.1 ms, System: 13.3 ms]
Range (min … max): 14.2 ms … 22.8 ms 162 runs
Benchmark 2: ./new_clang --version
Time (mean ± σ): 15.5 ms ± 1.4 ms [User: 3.6 ms, System: 11.8 ms]
Range (min … max): 12.4 ms … 20.3 ms 216 runs
Summary
'./new_clang --version' ran
1.13 ± 0.14 times faster than './old_clang --version'
```
We get about 2ms faster `--version` runs. While there is a lot of noise
in binary execution time, this delta is pretty consistent, and
represents over 10% improvement. This is particularly interesting to me
because for very short source files, repeatedly starting the `clang`
binary is actually the dominant cost. For example, `configure` scripts
running against the `clang` compiler are slow in large part because of
binary start up time, not the time to process the actual inputs to the
compiler.
----
This PR implements the string tables using `constexpr` code and the
existing macro system. I understand that the builtins are moving towards
a TableGen model, and if complete that would provide more options for
modeling this. Unfortunately, that migration isn't complete, and even
the parts that are migrated still rely on the ability to break out of
the TableGen model and directly expand an X-macro style `BUILTIN(...)`
textually. I looked at trying to complete the move to TableGen, but it
would both require the difficult migration of the remaining targets, and
solving some tricky problems with how to move away from any macro-based
expansion.
I was also able to find a reasonably clean and effective way of doing
this with the existing macros and some `constexpr` code that I think is
clean enough to be a pretty good intermediate state, and maybe give a
good target for the eventual TableGen solution. I was also able to
factor the macros into set of consistent patterns that avoids a
significant regression in overall boilerplate.
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|
Revision tags: llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
|
#
c91b50ed |
| 09-Jul-2024 |
Brian Cain <bcain@quicinc.com> |
[hexagon] Add {con,de}structive interference size defn (#94877)
This support was originally added in 72c373bfdc98 ([C++17] Support
__GCC_[CON|DE]STRUCTIVE_SIZE (#89446), 2024-04-26). We're overridi
[hexagon] Add {con,de}structive interference size defn (#94877)
This support was originally added in 72c373bfdc98 ([C++17] Support
__GCC_[CON|DE]STRUCTIVE_SIZE (#89446), 2024-04-26). We're overriding the
values for Hexagon here.
Signed-off-by: Brian Cain <bcain@quicinc.com>
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|
Revision tags: llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5 |
|
#
78bf8a0a |
| 17-May-2023 |
John Brawn <john.brawn@arm.com> |
[clang] Don't define predefined macros multiple times
Fix several instances of macros being defined multiple times in several targets. Most of these are just simple duplication in a TargetInfo or OS
[clang] Don't define predefined macros multiple times
Fix several instances of macros being defined multiple times in several targets. Most of these are just simple duplication in a TargetInfo or OSTargetInfo of things already defined in InitializePredefinedMacros or InitializeStandardPredefinedMacros, but there are a few that aren't: * AArch64 defines a couple of feature macros for armv8.1a that are handled generically by getTargetDefines. * CSKY needs to take care when CPUName and ArchName are the same. * Many os/target combinations result in __ELF__ being defined twice. Instead define __ELF__ just once in InitPreprocessor based on the Triple, which already knows what the object format is based on os and target.
These changes shouldn't change the final result of which macros are defined, with the exception of the changes to __ELF__ where if you explicitly specify the object type in the triple then this affects if __ELF__ is defined, e.g. --target=i686-windows-elf results in it being defined where it wasn't before, but this is more accurate as an ELF file is in fact generated.
Differential Revision: https://reviews.llvm.org/D150966
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|
Revision tags: llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init |
|
#
5a7f47cc |
| 17-Jan-2023 |
serge-sans-paille <sguelton@mozilla.com> |
[clang] Optimize clang::Builtin::Info density
Reorganize clang::Builtin::Info to have them naturally align on 4 bytes boundaries.
Instead of storing builtin headers as a straight char pointer, enum
[clang] Optimize clang::Builtin::Info density
Reorganize clang::Builtin::Info to have them naturally align on 4 bytes boundaries.
Instead of storing builtin headers as a straight char pointer, enumerate them and store the enum. It allows to use a small enum instead of a pointer to reference them.
On a 64 bit machine, this brings sizeof(clang::Builtin::Info) from 56 down to 48 bytes.
On a release build on my Linux 64 bit machine, it shrinks the size of libclang-cpp.so by 193kB.
The impact on performance is negligible in terms of instruction count, but the wall time seems better, see https://llvm-compile-time-tracker.com/compare.php?from=b3d8639f3536a4876b511aca9fb7948ff9266cee&to=a89b56423f98b550260a58c41e64aff9e56b76be&stat=task-clock
Differential Revision: https://reviews.llvm.org/D142024
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Revision tags: llvmorg-15.0.7 |
|
#
a3c248db |
| 06-Jan-2023 |
serge-sans-paille <sguelton@mozilla.com> |
Move from llvm::makeArrayRef to ArrayRef deduction guides - clang/ part
This is a follow-up to https://reviews.llvm.org/D140896, split into several parts as it touches a lot of files.
Differential
Move from llvm::makeArrayRef to ArrayRef deduction guides - clang/ part
This is a follow-up to https://reviews.llvm.org/D140896, split into several parts as it touches a lot of files.
Differential Revision: https://reviews.llvm.org/D141139
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|
#
d227c3b6 |
| 05-Jan-2023 |
Brad Smith <brad@comstyle.com> |
[Hexagon][VE][WebAssembly] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Reviewed By: kparzysz, aheejin, MaskRay
Differential Revision: https://revi
[Hexagon][VE][WebAssembly] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros
Reviewed By: kparzysz, aheejin, MaskRay
Differential Revision: https://reviews.llvm.org/D140757
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|
#
d9ab3e82 |
| 26-Dec-2022 |
serge-sans-paille <sguelton@mozilla.com> |
[clang] Use a StringRef instead of a raw char pointer to store builtin and call information
This avoids recomputing string length that is already known at compile time.
It has a slight impact on pr
[clang] Use a StringRef instead of a raw char pointer to store builtin and call information
This avoids recomputing string length that is already known at compile time.
It has a slight impact on preprocessing / compile time, see
https://llvm-compile-time-tracker.com/compare.php?from=3f36d2d579d8b0e8824d9dd99bfa79f456858f88&to=e49640c507ddc6615b5e503144301c8e41f8f434&stat=instructions:u
This a recommit of e953ae5bbc313fd0cc980ce021d487e5b5199ea4 and the subsequent fixes caa713559bd38f337d7d35de35686775e8fb5175 and 06b90e2e9c991e211fecc97948e533320a825470.
The above patchset caused some version of GCC to take eons to compile clang/lib/Basic/Targets/AArch64.cpp, as spotted in aa171833ab0017d9732e82b8682c9848ab25ff9e. The fix is to make BuiltinInfo tables a compilation unit static variable, instead of a private static variable.
Differential Revision: https://reviews.llvm.org/D139881
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Revision tags: llvmorg-15.0.6 |
|
#
7c476697 |
| 17-Nov-2022 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Add clang flags for v71, v71t, v73
|
Revision tags: llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
|
#
1d1b5efd |
| 23-Dec-2021 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Driver/preprocessor options for Hexagon v69
|
Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2 |
|
#
0577f4b1 |
| 14-Jun-2021 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Add HVX and control register names to Hexagon target
|
Revision tags: llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4 |
|
#
c539be1d |
| 11-Mar-2021 |
Sid Manning <sidneym@quicinc.com> |
[Hexagon] Add support for named registers cs0 and cs1
Allow inline assembly code to referece cs0 and cs1.
|
Revision tags: llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3 |
|
#
bc097f64 |
| 03-Feb-2021 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Add clang builtin definitions for Hexagon V68
|
Revision tags: llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2 |
|
#
7406eb4f |
| 10-Aug-2020 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Avoid creating an empty target feature
If the CPU string is empty, the target feature map may end up having an empty string inserted to it. The symptom of the problem is a warning message:
[Hexagon] Avoid creating an empty target feature
If the CPU string is empty, the target feature map may end up having an empty string inserted to it. The symptom of the problem is a warning message: '+' is not a recognized feature for this target (ignoring feature) Also, the target-features attribute in the module will have an empty string in it.
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|
Revision tags: llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3 |
|
#
d37cbda5 |
| 21-Feb-2020 |
Sid Manning <sidneym@quicinc.com> |
[Hexagon] Define __ELF__ by default.
Differential Revision: https://reviews.llvm.org/D74972
|
Revision tags: llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init |
|
#
305bf5b2 |
| 13-Jan-2020 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Add support for Hexagon v67t microarchitecture (tiny core)
|
#
c12a5917 |
| 17-Jan-2020 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Add support for Hexagon/HVX v67 ISA
|
#
6f3effbb |
| 16-Jan-2020 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Update autogenerated intrinsic info in clang
In addition to that, use target features to validate intrinsic availability on a given target.
|
Revision tags: llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1 |
|
#
99f51960 |
| 28-Oct-2019 |
Krzysztof Parzyszek <kparzysz@quicinc.com> |
[Hexagon] Handle remaining registers in getRegisterByName()
This fixes https://llvm.org/PR43829.
|
Revision tags: llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3, llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1 |
|
#
2946cd70 |
| 19-Jan-2019 |
Chandler Carruth <chandlerc@gmail.com> |
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license.
We understand that people may be surprised that we're moving the header entirely to discuss the ne
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license.
We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach.
Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository.
llvm-svn: 351636
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|
Revision tags: llvmorg-7.0.1, llvmorg-7.0.1-rc3 |
|
#
85393b28 |
| 05-Dec-2018 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Add support for Hexagon V66
llvm-svn: 348415
|
Revision tags: llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1 |
|
#
57e6706e |
| 19-Oct-2018 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
[Hexagon] Remove support for V4
llvm-svn: 344786
|