Revision tags: llvmorg-21-init |
|
#
4294fe17 |
| 20-Jan-2025 |
Brad Smith <brad@comstyle.com> |
[Driver][FreeBSD] Remove FreeBSD/loongarch32 support (#122515)
FreeBSD going forward will not have 32-bit arch support.
Also missed a spot with removing riscv32 support.
|
Revision tags: llvmorg-19.1.7 |
|
#
8a1174f0 |
| 10-Jan-2025 |
Ian Anderson <iana@apple.com> |
[Darwin][Driver][clang] arm64-apple-none-macho is missing the Apple macros from arm-apple-none-macho (#122427)
arm-apple-none-macho uses DarwinTargetInfo which provides several Apple
specific macro
[Darwin][Driver][clang] arm64-apple-none-macho is missing the Apple macros from arm-apple-none-macho (#122427)
arm-apple-none-macho uses DarwinTargetInfo which provides several Apple
specific macros. arm64-apple-none-macho however just uses the generic
AArch64leTargetInfo and doesn't get any of those macros. It's not clear
if everything from DarwinTargetInfo is desirable for
arm64-apple-none-macho, so make an AppleMachOTargetInfo to hold the
generic Apple macros and a few other basic things.
show more ...
|
#
d2498afc |
| 10-Jan-2025 |
Brad Smith <brad@comstyle.com> |
[Driver][NFC] Formatting fixes (#122519)
|
#
2d6e7c2b |
| 25-Dec-2024 |
Alexey Gerenkov <alexey@espressif.com> |
[Clang][Xtensa] Add Xtensa target. (#118008)
This PR implements support for generic Xtensa target in CLang.
Co-authored-by: Andrei Safronov <safronov@espressif.com>
|
#
970f65a9 |
| 25-Dec-2024 |
Hervé Poussineau <hpoussin@reactos.org> |
[Clang][MIPS] Create specific targets for MIPS PE/COFF (#121040)
Implement GNU and MSVC variants.
When using them, _WIN32 and _M_MRX000/_MIPS_ macros are correctly
defined.
|
Revision tags: llvmorg-19.1.6 |
|
#
3b10e31d |
| 13-Dec-2024 |
hitmoon <zxq_yx_007@163.com> |
[clang][LoongArch] Add FreeBSD targets (#119191)
Add support for freebsd on loongarch
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Co-authored-by: yu shan wei <mpysw@vip.163.com>
|
Revision tags: llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3 |
|
#
af7c58b7 |
| 28-Oct-2024 |
Aaron Ballman <aaron@aaronballman.com> |
Remove support for RenderScript (#112916)
See
https://discourse.llvm.org/t/rfc-deprecate-and-eventually-remove-renderscript-support/81284
for the RFC
|
Revision tags: llvmorg-19.1.2, llvmorg-19.1.1 |
|
#
fb784953 |
| 20-Sep-2024 |
Prabhuk <prabhukr@google.com> |
Reland "[Driver] Add toolchain for X86_64 UEFI target" (#109364)
Reverts llvm/llvm-project#109340
Addressing the failed MAC Clang Driver test as part of this reland.
|
#
d2df2e41 |
| 19-Sep-2024 |
Prabhuk <prabhukr@google.com> |
Revert "[Driver] Add toolchain for X86_64 UEFI target" (#109340)
Reverts llvm/llvm-project#76838
Appears to be causing failures in MAC builders. First reverting the
patch and will investigate af
Revert "[Driver] Add toolchain for X86_64 UEFI target" (#109340)
Reverts llvm/llvm-project#76838
Appears to be causing failures in MAC builders. First reverting the
patch and will investigate after.
show more ...
|
#
d1335fb8 |
| 19-Sep-2024 |
Prabhuk <prabhukr@google.com> |
[Driver] Add toolchain for X86_64 UEFI target (#76838)
Introduce changes necessary for UEFI X86_64 target Clang driver.
Addressed the review comments originally suggested in Phabricator.
Differe
[Driver] Add toolchain for X86_64 UEFI target (#76838)
Introduce changes necessary for UEFI X86_64 target Clang driver.
Addressed the review comments originally suggested in Phabricator.
Differential Revision: https://reviews.llvm.org/D159541
show more ...
|
Revision tags: llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3 |
|
#
617cf8a7 |
| 06-Aug-2024 |
Aaron Ballman <aaron@aaronballman.com> |
Reapply "Finish deleting the le32/le64 targets" (#99079) (#101983)
This reverts commit d3f8105c65046173e20c4c59394b4a7f1bbe7627.
Halide no longer relies on this target:
https://github.com/llvm/l
Reapply "Finish deleting the le32/le64 targets" (#99079) (#101983)
This reverts commit d3f8105c65046173e20c4c59394b4a7f1bbe7627.
Halide no longer relies on this target:
https://github.com/llvm/llvm-project/pull/98497#issuecomment-2253358685
show more ...
|
Revision tags: llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init |
|
#
d3f8105c |
| 16-Jul-2024 |
Aaron Ballman <aaron@aaronballman.com> |
Revert "Finish deleting the le32/le64 targets" (#99079)
Reverts llvm/llvm-project#98497
We're reverting this for approx 30 days so that the Halide project has
time to transition off the target.
|
#
2369a54f |
| 12-Jul-2024 |
Aaron Ballman <aaron@aaronballman.com> |
Finish deleting the le32/le64 targets (#98497)
This is a revert of ef5e7f90ea4d5063ce68b952c5de473e610afc02 which was a
temporary partial revert of 77ac823fd285973cfb3517932c09d82e6a32f46d.
The le
Finish deleting the le32/le64 targets (#98497)
This is a revert of ef5e7f90ea4d5063ce68b952c5de473e610afc02 which was a
temporary partial revert of 77ac823fd285973cfb3517932c09d82e6a32f46d.
The le32 and le64 targets are no longer necessary to retain, so this
removes them entirely.
show more ...
|
Revision tags: llvmorg-18.1.8 |
|
#
88e2bb40 |
| 07-Jun-2024 |
Alex Voicu <alexandru.voicu@amd.com> |
[clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (#89796)
This change seeks to add support for vendor flavoured SPIRV - more
specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV
[clang][SPIR-V] Add support for AMDGCN flavoured SPIRV (#89796)
This change seeks to add support for vendor flavoured SPIRV - more
specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that
carries some extra bits of information that are only usable by AMDGCN
targets, forfeiting absolute genericity to obtain greater expressiveness
for target features:
- AMDGCN inline ASM is allowed/supported, under the assumption that the
[SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc)
extension is enabled/used
- AMDGCN target specific builtins are allowed/supported, under the
assumption that e.g. the `--spirv-allow-unknown-intrinsics` option is
enabled when using the downstream translator
- the featureset matches the union of AMDGCN targets' features
- the datalayout string is overspecified to affix both the program
address space and the alloca address space, the latter under the
assumption that the
[SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc)
extension is enabled/used, case in which the extant SPIRV datalayout
string would lead to pointers to function pointing to the private
address space, which would be wrong.
Existing AMDGCN tests are extended to cover this new target. It is
currently dormant / will require some additional changes, but I thought
I'd rather put it up for review to get feedback as early as possible. I
will note that an alternative option is to place this under AMDGPU, but
that seems slightly less natural, since this is still SPIRV, albeit
relaxed in terms of preconditions & constrained in terms of
postconditions, and only guaranteed to be usable on AMDGCN targets (it
is still possible to obtain pristine portable SPIRV through usage of the
flavoured target, though).
show more ...
|
Revision tags: llvmorg-18.1.7, llvmorg-18.1.6 |
|
#
6d890148 |
| 08-May-2024 |
S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli@microsoft.com> |
[DXIL] Set DXIL Version in DXIL target triple based on shader model version (#91407)
This change set restores commit 080978dd2067d0c9ea7e229aa7696c2480d89ef1 that was reverted to address ASAN
failu
[DXIL] Set DXIL Version in DXIL target triple based on shader model version (#91407)
This change set restores commit 080978dd2067d0c9ea7e229aa7696c2480d89ef1 that was reverted to address ASAN
failures and includes a fix for the ASAN failures.
Following is the description of the change:
An earlier commit provided a way to decouple DXIL version from Shader
Model version by representing the DXIL version as `SubArch` in the DXIL
Target Triple and adding corresponding valid DXIL Arch types.
This change constructs DXIL target triple with DXIL version that is
deduced from Shader Model version specified in the following scenarios:
1. When compilation target profile is specified:
For e.g., DXIL target triple `dxilv1.8-unknown-shader6.8-library` is
constructed when `-T lib_6_8` is specified.
2. When DXIL target triple without DXIL version is specified:
For e.g., DXIL target triple `dxilv1.8-pc-shadermodel6.8-library` is
constructed when `-mtriple=dxil-pc-shadermodel6.8-library` is specified.
Updated relevant HLSL tests that check for target triple.
show more ...
|
#
178ff395 |
| 07-May-2024 |
S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli@microsoft.com> |
Revert "[DirectX][DXIL] Set DXIL Version in DXIL target triple based on shader model version" (#91290)
Reverts llvm/llvm-project#90809
Need to investigate ASAN failures.
|
#
080978dd |
| 06-May-2024 |
S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli@microsoft.com> |
[DirectX][DXIL] Set DXIL Version in DXIL target triple based on shader model version (#90809)
An earlier commit provided a way to decouple DXIL version from Shader
Model version by representing the
[DirectX][DXIL] Set DXIL Version in DXIL target triple based on shader model version (#90809)
An earlier commit provided a way to decouple DXIL version from Shader
Model version by representing the DXIL version as `SubArch` in the DXIL
Target Triple and adding corresponding valid DXIL Arch types.
This change constructs DXIL target triple with DXIL version that is
deduced from Shader Model version specified in the following scenarios:
1. When compilation target profile is specified:
For e.g., DXIL target triple `dxilv1.8-unknown-shader6.8-library` is
constructed when `-T lib_6_8` is specified.
2. When DXIL target triple without DXIL version is specified:
For e.g., DXIL target triple `dxilv1.8-pc-shadermodel6.8-library` is
constructed when `-mtriple=dxil-pc-shadermodel6.8-library` is specified.
Updated relevant HLSL tests that check for target triple.
Validated that Clang (`check-clang`) and LLVM (`check-llvm`) regression
tests pass.
show more ...
|
Revision tags: llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3 |
|
#
ea9ec80b |
| 17-Feb-2024 |
Prabhuk <prabhukr@google.com> |
Revert "[AArch64] Add soft-float ABI (#74460)" (#82032)
This reverts commit 9cc98e336980f00cbafcbed8841344e6ac472bdc.
Issue: https://github.com/ClangBuiltLinux/linux/issues/1997
|
#
9cc98e33 |
| 15-Feb-2024 |
ostannard <oliver.stannard@arm.com> |
[AArch64] Add soft-float ABI (#74460)
This adds support for the AArch64 soft-float ABI. The specification for
this ABI was added by https://github.com/ARM-software/abi-aa/pull/232.
Because all e
[AArch64] Add soft-float ABI (#74460)
This adds support for the AArch64 soft-float ABI. The specification for
this ABI was added by https://github.com/ARM-software/abi-aa/pull/232.
Because all existing AArch64 hardware has floating-point hardware, we
expect this to be a niche option, only used for embedded systems on
R-profile systems. We are going to document that SysV-like systems
should only ever use the base (hard-float) PCS variant:
https://github.com/ARM-software/abi-aa/pull/233. For that reason, I've
not added an option to select the ABI independently of the FPU hardware,
instead the new ABI is enabled iff the target architecture does not have
an FPU.
For testing, I have run this through an ABI fuzzer, but since this is
the first implementation it can only test for internal consistency
(callers and callees agree on the PCS), not for conformance to the ABI
spec.
show more ...
|
Revision tags: llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init |
|
#
4fffb040 |
| 17-Jan-2024 |
Samuel Thibault <samuel.thibault@ens-lyon.org> |
Hurd: Add x86_64 support (#78065)
This adds Hurd toolchain support to Clang's driver in addition to
handling
translating the triple from GCC toolchain-compatible form (x86_64-gnu)
to
the actual
Hurd: Add x86_64 support (#78065)
This adds Hurd toolchain support to Clang's driver in addition to
handling
translating the triple from GCC toolchain-compatible form (x86_64-gnu)
to
the actual triple registered in LLVM (x86_64-pc-hurd-gnu).
show more ...
|
Revision tags: llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4 |
|
#
15254eb7 |
| 26-Oct-2023 |
Brad Smith <brad@comstyle.com> |
[Driver] Clean up unused architecture related bits for *BSD's (#69809)
- FreeBSD removed big-endian arm with 12.0.
- OpenBSD never had big-endian arm support. I added it just in case, but it has
[Driver] Clean up unused architecture related bits for *BSD's (#69809)
- FreeBSD removed big-endian arm with 12.0.
- OpenBSD never had big-endian arm support. I added it just in case, but it has
never been used.
- Remove sparcel bits. It was sprinkled in a few places but it will never be a
thing.
- Remove 32-bit sparc bits for FreeBSD. FreeBSD has never had 32-bit sparc
support.
- Remove sparc64 IAS test as support was enabled across the board awhile ago.
show more ...
|
Revision tags: llvmorg-17.0.3 |
|
#
7cfe32d4 |
| 09-Oct-2023 |
Brad Smith <brad@comstyle.com> |
[Driver] Hook up Haiku ARM support (#67222)
|
Revision tags: llvmorg-17.0.2 |
|
#
c1300efc |
| 25-Sep-2023 |
Brad Smith <brad@comstyle.com> |
[Driver] Remove FreeBSD/riscv32 support (#67277)
FreeBSD does not support riscv32 and has no intention of doing so.
|
#
62ffbe0d |
| 24-Sep-2023 |
Brad Smith <brad@comstyle.com> |
[Driver] Hook up NetBSD/riscv support (#67256)
|
Revision tags: llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
|
#
53b6a169 |
| 21-Jul-2023 |
Nathan Gauër <brioche@google.com> |
[SPIR-V] Add SPIR-V logical triple.
Clang implements SPIR-V with both Physical32 and Physical64 addressing models. This commit adds a new triple value for the Logical addressing model.
Differential
[SPIR-V] Add SPIR-V logical triple.
Clang implements SPIR-V with both Physical32 and Physical64 addressing models. This commit adds a new triple value for the Logical addressing model.
Differential Revision: https://reviews.llvm.org/D155978
show more ...
|