History log of /isa-l_crypto/include/multibinary.asm (Results 1 – 7 of 7)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: v2.25.0
# 86058544 12-Feb-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.c

Fix a handful of spelling mistakes and typos

Fixed outstanding spelling mistakes and typos in comments and
variables found using codespell

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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Revision tags: v2.24.0, v2.23.0
# 0e4f088a 22-Sep-2020 Greg Tucker <greg.b.tucker@intel.com>

build: Fix for nasm on windows and osx

Windows and osx build can only use yasm because some procedural items such as
proc_start and symbol types were not supported by nasm there. This adds a few
ma

build: Fix for nasm on windows and osx

Windows and osx build can only use yasm because some procedural items such as
proc_start and symbol types were not supported by nasm there. This adds a few
macros and fixes for nasm to get around this.

Change-Id: Ib8d3f93f69cba06e36a62c46e65163ab80553072
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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# dcce8ecb 19-Oct-2019 Greg Tucker <greg.b.tucker@intel.com>

fix: Define for cpuid7_ebx check to more correct name

Just changes the define name FLAGS_CPUID7_EBX_AVX512_G1 to not refer to the
incorrect ecx. The comparisons are already against the correct regis

fix: Define for cpuid7_ebx check to more correct name

Just changes the define name FLAGS_CPUID7_EBX_AVX512_G1 to not refer to the
incorrect ecx. The comparisons are already against the correct register but
this avoids confusion.

Change-Id: I5b3d81ece61db885c17d09bbf8996dc1d8bb88e9
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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# 8dc5d913 19-Oct-2019 Greg Tucker <greg.b.tucker@intel.com>

build: Add multi-binary checking for new arch

Port of isa-l 198b026a552b of same name.

Change-Id: I7f37299d62ebc909401c59f9773e298a3e34391d
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
Sign

build: Add multi-binary checking for new arch

Port of isa-l 198b026a552b of same name.

Change-Id: I7f37299d62ebc909401c59f9773e298a3e34391d
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Revision tags: v2.22.0, v2.21.0, v2.20.0, v2.19.0
# 30604006 26-May-2017 Xiaodong Liu <xiaodong.liu@intel.com>

sha1-mb: add shani for Goldmont and Cannonlake

1. Add sse_ni functions for Denverton
2. Add avx512_ni functions for Cannonlake
3. Add a flush test case
4. Update versions

Change-Id: I546020f083d374

sha1-mb: add shani for Goldmont and Cannonlake

1. Add sse_ni functions for Denverton
2. Add avx512_ni functions for Cannonlake
3. Add a flush test case
4. Update versions

Change-Id: I546020f083d374137f877a8cb3574139daf17be0
Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>

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# cc0c2aef 31-May-2017 Greg Tucker <greg.b.tucker@intel.com>

Format only patch from iindent and remove_whitespace

Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>


Revision tags: v2.18.0
# 6df3ef80 04-May-2016 Greg Tucker <greg.b.tucker@intel.com>

Add multi-buffer hashing

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>