mem: fix compilation with YASM

Fixes #294.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mem: fix build on FreeBSD

Fix build warnings on FreeBSD, due to unused value.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

mem: reformat using new code style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

mem_zero_detect_test: fix for issue reported by static code analysis

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

mem: [test] fix memory leak

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

lib: reduce verbosity by default in tests

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher u

Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher using sysctlbyname
- Use __USER_LABEL_PREFIX__
- Use __TEXT,__const as readonly section
- use ASM_DEF_RODATA macro
- fix func decl

Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

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Add AVX512 implementation of mem_zero_detect().

Change-Id: I60fe0846d783787198b6a44a090fd9fe17c1807f
Signed-off-by: Nicola Torracca <shark@bitchx.it>

Fix s390 build

The goal of this patch is to make isa-l testsuite pass on s390 with
minimal changes to the library. The one and only reason isa-l does not
work on s390 at the moment is that s390 is b

Fix s390 build

The goal of this patch is to make isa-l testsuite pass on s390 with
minimal changes to the library. The one and only reason isa-l does not
work on s390 at the moment is that s390 is big-endian, and isa-l
assumes little-endian at a lot of places.

There are two flavors of this: loading/storing integers from/to
memory, and overlapping structs. Loads/stores are already helpfully
wrapped by unaligned.h header, so replace the functions there with
endianness-aware variants. Solve struct member overlap by reversing
their order on big-endian.

Also, fix a couple of usages of uninitialized memory in the testsuite
(found with MemorySanitizer).

Fixes s390x part of #188.

Change-Id: Iaf14a113bd266900192cc8b44212f8a47a8c7753
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>

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mem: Add small allocs into test to help mem checkers

Change-Id: I6de3951ff66a715d8b1c0f36d691cb60e8396139
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

mem: Move new mem_zero_detect function to avx2

New mem_zero_detect function will fail on avx only machines.

Change-Id: I3bca49bff886f9c130c89e8c74b31110e9bac76b
Signed-off-by: Greg Tucker <greg.b.t

mem: Move new mem_zero_detect function to avx2

New mem_zero_detect function will fail on avx only machines.

Change-Id: I3bca49bff886f9c130c89e8c74b31110e9bac76b
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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mem_zero_detect_avx: OR multiple vector and test for non zero on the result

micro-optimizations: vpcmpeqb+vpmaskmov is faster than vptest according
to uops.info; make usually untaken branches target

mem_zero_detect_avx: OR multiple vector and test for non zero on the result

micro-optimizations: vpcmpeqb+vpmaskmov is faster than vptest according
to uops.info; make usually untaken branches target forward.
reduce numbers of data dependant branches and code size.

Change-Id: Ie70b4bc99685368e5131f23344348bfaf7c27d3e
Signed-off-by: Nicola Torracca <shark@bitchx.it>

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build: Remove unneeded file types.h

The file types.h has long been misnamed and overlaps with
functionality in the test helper routines.

Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195
Signed-

build: Remove unneeded file types.h

The file types.h has long been misnamed and overlaps with
functionality in the test helper routines.

Change-Id: I774047d3a0074198b67a6b4e909f1e2ce1938195
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
funct

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes s

build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes so
nasm can be used to build on windows.

Change-Id: Ia05dc3ff482f33b0f915bb1be3c7df5e4a753b3a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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enable VSX SIMD in ISA-L for ppc64le

1) Implement the ErasureCode function in Altivec Intrinsics
2) Coding style update

Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
Thanks-to: Daniel Ax

enable VSX SIMD in ISA-L for ppc64le

1) Implement the ErasureCode function in Altivec Intrinsics
2) Coding style update

Change-Id: I2c81d035f4083e9b011dbf3b741f628813b68606
Thanks-to: Daniel Axtens <dja@axtens.net>
Signed-off-by: Hong Bo Peng <penghb@cn.ibm.com>

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multibinary: Add run-time cpu feature detect for aarch64

Some CPUs report "illegal instruction" error for the crc test because
they do not support the relevant optional feature . This can be fixed

multibinary: Add run-time cpu feature detect for aarch64

Some CPUs report "illegal instruction" error for the crc test because
they do not support the relevant optional feature . This can be fixed by
introducing CPU feature detection for AArch64 .

The difference with the x86 implementation is the dispatcher . It is based
on the glibc function `getauxval(AT_HWCAP)` and `getauxval(AT_HWCAP2)` , not
registers or instructions .

On a heterogeneous system (big.LITTLE) , it is dangerous to detect CPU
features using identification registers . And while it is possible to use
architectural feature registers from userspace on recent kernels, this
won't necessarily work with older platforms . Thus we use the HW_CAPs
exported from the kernel (and visible in getauxval) as the solution.

- According to kernel suggestion , getauxval should be used for this purpose .
- [CPU Feature detection](https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst)
- According to AAPCS result/paramter registers should be saved/restore for function call
- [AAPCS](http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf)
- [GLibc](https://sourceware.org/git/gitweb.cgi?p=glibc.git;a=blob;f=sysdeps/aarch64/dl-trampoline.S)

Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
Change-Id: Ic9abe0d2268ac95537e1abf10acc642fc58a5054

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all: Revamp performance testing to be time based

Change-Id: I6260d28e4adc974d8db0a1c770e3eb922d87f8e4
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

mem: Remove unaligned loads in base function

Change-Id: I8fb0f2e2e372485c864d5c60f816b661a865b707
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

mem: Change test r and l data type to avoid unsigned add overflow

Change-Id: If9c30c5fda72ed5139a7cab01b5236f57a3ad0ef
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

aarch64: Fix dynamic lib call crash

If an application treats these functions as function pointers, and this
lib (isa-l) is compiled into solib, a segmentation fault may occur.

For example: Ubuntu 1

aarch64: Fix dynamic lib call crash

If an application treats these functions as function pointers, and this
lib (isa-l) is compiled into solib, a segmentation fault may occur.

For example: Ubuntu 16.04 on arm64 platfrom will be crash, because the
linker does not know that this symbol is a function, so mark the function
type explicitly with %function to solves this issue.

Change-Id: Iba41b1f1367146d7dcce09203694b08b1cb8ec20
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

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mem: mem-zero-detect optimization on Arm64

Change-Id: I9e7b8c80657c9c251d69efcfc73acc53567cfa33
Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>

build: Add aarch64 support

Change-Id: If9594936a28355d89edd1a331b3b429dffa44184
Signed-off-by: Yibo Cai <yibo.cai@arm.com>

build: Fix for mac nasm lack of symbol types

Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

mem: Fix zero detect base function for mingw

Mingw does not define WORDSIZE and incorrect int width was used.

Change-Id: Idc9f560dd1c722d51f6e54ba2342feafa13f8fa5
Signed-off-by: Greg Tucker <greg.b

mem: Fix zero detect base function for mingw

Mingw does not define WORDSIZE and incorrect int width was used.

Change-Id: Idc9f560dd1c722d51f6e54ba2342feafa13f8fa5
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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