Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by

Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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lib: add new interface supporting AVX2 with GFNI

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
funct

x86: Add ENDBR32/ENDBR64 at function entries for Intel CET

To support Intel CET, all indirect branch targets must start with
ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to
function entries in x86 assembly codes which are indirect branch
targets as discovered by running testsuite on Intel CET machine and
visual inspection.

Verified with

$ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux
$ make -j8
$ make -j8 check

with both nasm and yasm on both CET and non-CET machines.

Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

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build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes s

build: Fix for windows to allow nasm use

Previously windows build could only use yasm because some procedural items such
as proc_start were not supported by nasm. This adds a few macros and fixes so
nasm can be used to build on windows.

Change-Id: Ia05dc3ff482f33b0f915bb1be3c7df5e4a753b3a
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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crc: Add new vclmul version of gzip_refl

Change-Id: I8050853dcd177f4fb506f32f5fa723f7a1d3cded
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

crc: Add vec version of crc32_gzip_refl when avx avail

Change-Id: I4a069c318c809dcd21a6ebc47d3e0d1c131599ea
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

build: Set assembler feature level in std make

Also fix multibinary to try each available arch

Change-Id: Icd8496d169665bded478a33a02e739d1f8349b6f
Signed-off-by: Greg Tucker <greg.b.tucker@intel.c

build: Set assembler feature level in std make

Also fix multibinary to try each available arch

Change-Id: Icd8496d169665bded478a33a02e739d1f8349b6f
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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build: Add multi-binary checking for new arch

Change-Id: I8bb8d9e9ae28987ee583976871ff84ee205bdbdc
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

build: Setup as_feature_level

Change-Id: I7443058c577cf8eafe10acc2b2bfdfe76e2ce264
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

build: Avoid requiring AVX512 define when using dispatch functions

Change-Id: I76af2d6ab7eb61ae531bbc7427650d08737c20ab
Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>

build: Fix for mac nasm lack of symbol types

Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

Format only patch from iindent and remove_whitespace

Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

crc64: add jones and iso format, crc64 code clean

1. Add normal and reflected bits order functions for ISO format and
Jones coefficients format.
2. Add a multi-binary macro for crc64 functions.
3

crc64: add jones and iso format, crc64 code clean

1. Add normal and reflected bits order functions for ISO format and
Jones coefficients format.
2. Add a multi-binary macro for crc64 functions.
3. In order to decrease number of repeated test.c and perf.c files,
using crc64_funcs_test.c and cr crc64_funcs_perf.c.
4. Add crc64_example.c to take the demonstration role.

Change-Id: Icb8c14f1a84cd98f58eb12206ca605dea8a2cefb
Signed-off-by: Xiaodong Liu <xiaodong.liu@intel.com>

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Change common and igzip multibinary check from sse4.1 to sse4.2

SSE optimized compression function is using crc32 instruction that is in SSE 4.2
not SSE4.1 as stated. Fixes incorect choice on core

Change common and igzip multibinary check from sse4.1 to sse4.2

SSE optimized compression function is using crc32 instruction that is in SSE 4.2
not SSE4.1 as stated. Fixes incorect choice on core 2 duo that is SSE 4.1 only.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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Add avx512 versions of ec_encode_data

- Includes gf_nvect_dot_prod, gf_nvect_mad functions
- Change ec multibinary to use common macros
- Autoconf checks for nasm or yasm support and picks if ava

Add avx512 versions of ec_encode_data

- Includes gf_nvect_dot_prod, gf_nvect_mad functions
- Change ec multibinary to use common macros
- Autoconf checks for nasm or yasm support and picks if available
- Leave out compile of any avx512 code if assembler not available

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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