History log of /isa-l/igzip/ (Results 1 – 25 of 336)
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e3c2d24318-Jan-2025 Mattias Ellert <mattias.ellert@physics.uu.se>

Address compiler warnings on ppc64le and s390x

igzip/igzip_icf_body.c:7:1: warning: type of 'gen_icf_map_lh1' does not match original declaration [-Wlto-type-mismatch]
7 | gen_icf_map_lh1(struct

Address compiler warnings on ppc64le and s390x

igzip/igzip_icf_body.c:7:1: warning: type of 'gen_icf_map_lh1' does not match original declaration [-Wlto-type-mismatch]
7 | gen_icf_map_lh1(struct isal_zstream *, struct deflate_icf *, uint32_t);
| ^
igzip/igzip_base_aliases.c:177:1: note: return value type mismatch
177 | gen_icf_map_lh1(struct isal_zstream *stream, struct deflate_icf *matches_icf_lookup,
| ^
igzip/igzip_base_aliases.c:177:1: note: type 'void' should match type 'uint64_t'
igzip/igzip_base_aliases.c:177:1: note: 'gen_icf_map_lh1' was previously declared here
igzip/igzip_base_aliases.c:177:1: note: code may be misoptimized unless '-fno-strict-aliasing' is used
igzip/igzip_icf_body.c:9:1: warning: type of 'set_long_icf_fg' does not match original declaration [-Wlto-type-mismatch]
9 | set_long_icf_fg(uint8_t *, uint64_t, uint64_t, struct deflate_icf *);
| ^
igzip/igzip_base_aliases.c:170:1: note: type mismatch in parameter 2
170 | set_long_icf_fg(uint8_t *next_in, uint8_t *end_in, struct deflate_icf *match_lookup,
| ^
igzip/igzip_base_aliases.c:170:1: note: 'set_long_icf_fg' was previously declared here
igzip/igzip_base_aliases.c:170:1: note: code may be misoptimized unless '-fno-strict-aliasing' is used
igzip/igzip_base_aliases.c:62:1: warning: type of 'set_long_icf_fg_base' does not match original declaration [-Wlto-type-mismatch]
62 | set_long_icf_fg_base(uint8_t *next_in, uint8_t *end_in, struct deflate_icf *match_lookup,
| ^
igzip/igzip_icf_body.c:34:1: note: type mismatch in parameter 2
34 | set_long_icf_fg_base(uint8_t *next_in, uint64_t processed, uint64_t input_size,
| ^
igzip/igzip_icf_body.c:34:1: note: 'set_long_icf_fg_base' was previously declared here
igzip/igzip_icf_body.c:34:1: note: code may be misoptimized unless '-fno-strict-aliasing' is used
igzip/igzip_base_aliases.c:54:1: warning: type of 'adler32_base' does not match original declaration [-Wlto-type-mismatch]
54 | adler32_base(uint32_t init, const unsigned char *buf, uint64_t len);
| ^
igzip/adler32_base.c:34:1: note: type mismatch in parameter 3
34 | adler32_base(uint32_t adler32, uint8_t *start, uint32_t length)
| ^
igzip/adler32_base.c:34:1: note: type 'uint32_t' should match type 'uint64_t'
igzip/adler32_base.c:34:1: note: 'adler32_base' was previously declared here
igzip/adler32_base.c:34:1: note: code may be misoptimized unless '-fno-strict-aliasing' is used

Signed-off-by: Mattias Ellert <mattias.ellert@physics.uu.se>

show more ...

7ebc65ba28-May-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: fix build on FreeBSD

Fix build warnings on FreeBSD, due to unused value.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

55fbfabf19-Apr-2024 Marcel Cornu <marcel.d.cornu@intel.com>

igzip: reformat using new code style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>


/isa-l/.clang-format
/isa-l/.clang-format-ignore
/isa-l/.github/workflows/ci.yml
/isa-l/CONTRIBUTING.md
/isa-l/crc/aarch64/crc64_rocksoft.c
/isa-l/crc/aarch64/crc_aarch64_dispatcher.c
/isa-l/crc/crc16_t10dif_copy_perf.c
/isa-l/crc/crc16_t10dif_copy_test.c
/isa-l/crc/crc16_t10dif_op_perf.c
/isa-l/crc/crc16_t10dif_perf.c
/isa-l/crc/crc16_t10dif_test.c
/isa-l/crc/crc32_funcs_test.c
/isa-l/crc/crc32_gzip_refl_perf.c
/isa-l/crc/crc32_ieee_perf.c
/isa-l/crc/crc32_iscsi_perf.c
/isa-l/crc/crc64_base.c
/isa-l/crc/crc64_example.c
/isa-l/crc/crc64_funcs_perf.c
/isa-l/crc/crc64_funcs_test.c
/isa-l/crc/crc64_ref.h
/isa-l/crc/crc_base.c
/isa-l/crc/crc_base_aliases.c
/isa-l/crc/crc_ref.h
/isa-l/crc/crc_simple_test.c
/isa-l/erasure_code/aarch64/ec_aarch64_dispatcher.c
/isa-l/erasure_code/aarch64/ec_aarch64_highlevel_func.c
/isa-l/erasure_code/ec_base.c
/isa-l/erasure_code/ec_base.h
/isa-l/erasure_code/ec_base_aliases.c
/isa-l/erasure_code/ec_highlevel_func.c
/isa-l/erasure_code/erasure_code_base_perf.c
/isa-l/erasure_code/erasure_code_base_test.c
/isa-l/erasure_code/erasure_code_perf.c
/isa-l/erasure_code/erasure_code_test.c
/isa-l/erasure_code/erasure_code_update_perf.c
/isa-l/erasure_code/erasure_code_update_test.c
/isa-l/erasure_code/gen_rs_matrix_limits.c
/isa-l/erasure_code/gf_inverse_test.c
/isa-l/erasure_code/gf_vect_dot_prod_1tbl.c
/isa-l/erasure_code/gf_vect_dot_prod_base_test.c
/isa-l/erasure_code/gf_vect_dot_prod_perf.c
/isa-l/erasure_code/gf_vect_dot_prod_test.c
/isa-l/erasure_code/gf_vect_mad_test.c
/isa-l/erasure_code/gf_vect_mul_base_test.c
/isa-l/erasure_code/gf_vect_mul_perf.c
/isa-l/erasure_code/gf_vect_mul_test.c
/isa-l/erasure_code/ppc64le/ec_base_vsx.c
/isa-l/erasure_code/ppc64le/ec_base_vsx.h
/isa-l/erasure_code/ppc64le/gf_2vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_2vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_3vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_3vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_4vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_4vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_5vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_5vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_6vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_6vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_vect_dot_prod_vsx.c
/isa-l/erasure_code/ppc64le/gf_vect_mad_vsx.c
/isa-l/erasure_code/ppc64le/gf_vect_mul_vsx.c
/isa-l/examples/crc/crc_combine_example.c
/isa-l/examples/ec/ec_piggyback_example.c
/isa-l/examples/ec/ec_simple_example.c
aarch64/igzip_multibinary_aarch64_dispatcher.c
adler32_base.c
adler32_perf.c
bitbuf2.h
checksum32_funcs_test.c
checksum_test_ref.h
encode_df.c
encode_df.h
flatten_ll.c
flatten_ll.h
generate_custom_hufftables.c
generate_static_inflate.c
huff_codes.c
huff_codes.h
huffman.h
hufftables_c.c
igzip.c
igzip_base.c
igzip_base_aliases.c
igzip_build_hash_table_perf.c
igzip_checksums.h
igzip_example.c
igzip_file_perf.c
igzip_hist_perf.c
igzip_icf_base.c
igzip_icf_body.c
igzip_inflate.c
igzip_inflate_test.c
igzip_level_buf_structs.h
igzip_perf.c
igzip_rand_test.c
igzip_semi_dyn_file_perf.c
igzip_sync_flush_example.c
igzip_wrapper.h
igzip_wrapper_hdr_test.c
inflate_std_vects.h
proc_heap_base.c
repeated_char_result.h
static_inflate.h
/isa-l/tools/check_format.sh
/isa-l/tools/format.sh
38279f5e08-Mar-2024 Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

Avoid using x18 register

Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

4be96e2406-Mar-2024 Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

Fixed isal_deflate_icf_finish_lvl1 dispatcher

Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

1500db7523-Jan-2024 Colin Ian King <colin.i.king@gmail.com>

Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by

Fix a handful of spelling mistakes and typos

There are quite a few spelling mistakes and typos in comments and
user facing message literal strings as found using codespell. Fix
these.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

29d99fce20-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: add zlib header init function

Add isal_zlib_hdr_init() function to initialize
the isal_zlib_header structure to all 0.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

6ef2abe819-Dec-2023 Tomasz Kantecki <tomasz.kantecki@intel.com>

igzip: fix issues reported by static code analysis

compute_dist_code() and compute_dist_icf_code() in huffman.h:
Correct `assert(msb >= 1)` to `assert(msb >= 2)`.
`msb` cannot be lower than

igzip: fix issues reported by static code analysis

compute_dist_code() and compute_dist_icf_code() in huffman.h:
Correct `assert(msb >= 1)` to `assert(msb >= 2)`.
`msb` cannot be lower than 2 as it would result in corrupt computations.

get_dist_code() in huffman.h:
Remove dead `if` statement at the beginning of the function.
`dist` must be equal 1 or above in this function.

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

show more ...

5a00eaec14-Dec-2023 Tomasz Kantecki <tomasz.kantecki@intel.com>

igzip: several fixes for issues reported by static code analysis

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

c06db0c614-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: [test] fix memory leak

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

0e6bc4a505-Dec-2023 Tomasz Kantecki <tomasz.kantecki@intel.com>

igzip: zero `flags` field in isal_gzip_header_init()

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

4203d96205-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: fix null-terminated string setting

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

4a4635e805-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: remove unneeded check

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

02aa005c29-Nov-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: fix return value in wrapper header test

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

7e2b097f05-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: fix build warnings on Windows

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

2ca781df29-Nov-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

lib: reduce verbosity by default in tests

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>


/isa-l/Makefile.nmake
/isa-l/crc/crc16_t10dif_copy_test.c
/isa-l/crc/crc16_t10dif_test.c
/isa-l/crc/crc32_funcs_test.c
/isa-l/crc/crc64_funcs_test.c
/isa-l/erasure_code/Makefile.am
/isa-l/erasure_code/ec_base.c
/isa-l/erasure_code/ec_base.h
/isa-l/erasure_code/ec_base_aliases.c
/isa-l/erasure_code/ec_highlevel_func.c
/isa-l/erasure_code/ec_multibinary.asm
/isa-l/erasure_code/erasure_code_base_perf.c
/isa-l/erasure_code/erasure_code_base_test.c
/isa-l/erasure_code/erasure_code_perf.c
/isa-l/erasure_code/erasure_code_test.c
/isa-l/erasure_code/erasure_code_update_perf.c
/isa-l/erasure_code/erasure_code_update_test.c
/isa-l/erasure_code/gf_2vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_2vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_2vect_mad_avx512.asm
/isa-l/erasure_code/gf_2vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_3vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_3vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_3vect_mad_avx512.asm
/isa-l/erasure_code/gf_3vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_4vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_4vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_4vect_mad_avx512.asm
/isa-l/erasure_code/gf_4vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_5vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_5vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_5vect_mad_avx512.asm
/isa-l/erasure_code/gf_5vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_6vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_6vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_6vect_mad_avx512.asm
/isa-l/erasure_code/gf_6vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_inverse_test.c
/isa-l/erasure_code/gf_vect_dot_prod_avx2_gfni.asm
/isa-l/erasure_code/gf_vect_dot_prod_avx512.asm
/isa-l/erasure_code/gf_vect_dot_prod_avx512_gfni.asm
/isa-l/erasure_code/gf_vect_dot_prod_base_test.c
/isa-l/erasure_code/gf_vect_dot_prod_test.c
/isa-l/erasure_code/gf_vect_gfni.inc
/isa-l/erasure_code/gf_vect_mad_avx2_gfni.asm
/isa-l/erasure_code/gf_vect_mad_avx512.asm
/isa-l/erasure_code/gf_vect_mad_avx512_gfni.asm
/isa-l/erasure_code/gf_vect_mad_test.c
/isa-l/erasure_code/gf_vect_mul_base_test.c
/isa-l/erasure_code/gf_vect_mul_test.c
checksum32_funcs_test.c
igzip_rand_test.c
igzip_wrapper_hdr_test.c
/isa-l/include/erasure_code.h
/isa-l/include/memcpy.asm
/isa-l/include/multibinary.asm
/isa-l/include/reg_sizes.asm
/isa-l/isa-l.def
/isa-l/mem/mem_zero_detect_test.c
/isa-l/raid/pq_check_test.c
/isa-l/raid/pq_gen_test.c
/isa-l/raid/xor_check_test.c
/isa-l/raid/xor_gen_test.c
/isa-l/tools/test_extended.sh
e2acfbfe19-Sep-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

igzip: fix build warning

Fix the following build issue by initializing look_back_dist to 0.

igzip/igzip_inflate.c: In function ‘decode_huffman_code_block_stateless_base’:
igzip/igzip_inflate.c:1727

igzip: fix build warning

Fix the following build issue by initializing look_back_dist to 0.

igzip/igzip_inflate.c: In function ‘decode_huffman_code_block_stateless_base’:
igzip/igzip_inflate.c:1727:36:
warning: ‘look_back_dist’ may be used uninitialized [-Wmaybe-uninitialized]

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

9f2b68f014-Mar-2023 Greg Tucker <greg.b.tucker@intel.com>

igzip: Add precautionary reset hist_bits on stateless_init

The zstate.hist_bits is an option and shouldn't be set randomly by a
deflate stateless run but like level we may set anyway.

Change-Id: I3

igzip: Add precautionary reset hist_bits on stateless_init

The zstate.hist_bits is an option and shouldn't be set randomly by a
deflate stateless run but like level we may set anyway.

Change-Id: I37d3b51863d4697e964d45a482ddd526f40a0902
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

show more ...

1187583a21-Nov-2020 Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher u

Fixes for aarch64 mac

- It should be fine to enable pmull always on Apple Silicon
- macOS 12+ is required for PMULL instruction.
- Changed the conditional macro to __APPLE__
- Rewritten dispatcher using sysctlbyname
- Use __USER_LABEL_PREFIX__
- Use __TEXT,__const as readonly section
- use ASM_DEF_RODATA macro
- fix func decl

Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974
Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

show more ...


/isa-l/crc/aarch64/crc16_t10dif_copy_pmull.S
/isa-l/crc/aarch64/crc16_t10dif_pmull.S
/isa-l/crc/aarch64/crc32_aarch64_common.h
/isa-l/crc/aarch64/crc32_common_mix_neoverse_n1.S
/isa-l/crc/aarch64/crc32_gzip_refl_3crc_fold.S
/isa-l/crc/aarch64/crc32_gzip_refl_crc_ext.S
/isa-l/crc/aarch64/crc32_gzip_refl_pmull.S
/isa-l/crc/aarch64/crc32_gzip_refl_pmull.h
/isa-l/crc/aarch64/crc32_ieee_norm_pmull.S
/isa-l/crc/aarch64/crc32_ieee_norm_pmull.h
/isa-l/crc/aarch64/crc32_iscsi_3crc_fold.S
/isa-l/crc/aarch64/crc32_iscsi_crc_ext.S
/isa-l/crc/aarch64/crc32_iscsi_refl_pmull.S
/isa-l/crc/aarch64/crc32_iscsi_refl_pmull.h
/isa-l/crc/aarch64/crc32_mix_default.S
/isa-l/crc/aarch64/crc32_mix_default_common.S
/isa-l/crc/aarch64/crc32_mix_neoverse_n1.S
/isa-l/crc/aarch64/crc32_norm_common_pmull.h
/isa-l/crc/aarch64/crc32_refl_common_pmull.h
/isa-l/crc/aarch64/crc32c_mix_default.S
/isa-l/crc/aarch64/crc32c_mix_neoverse_n1.S
/isa-l/crc/aarch64/crc64_ecma_norm_pmull.S
/isa-l/crc/aarch64/crc64_ecma_norm_pmull.h
/isa-l/crc/aarch64/crc64_ecma_refl_pmull.S
/isa-l/crc/aarch64/crc64_ecma_refl_pmull.h
/isa-l/crc/aarch64/crc64_iso_norm_pmull.S
/isa-l/crc/aarch64/crc64_iso_norm_pmull.h
/isa-l/crc/aarch64/crc64_iso_refl_pmull.S
/isa-l/crc/aarch64/crc64_iso_refl_pmull.h
/isa-l/crc/aarch64/crc64_jones_norm_pmull.S
/isa-l/crc/aarch64/crc64_jones_norm_pmull.h
/isa-l/crc/aarch64/crc64_jones_refl_pmull.S
/isa-l/crc/aarch64/crc64_jones_refl_pmull.h
/isa-l/crc/aarch64/crc64_norm_common_pmull.h
/isa-l/crc/aarch64/crc64_refl_common_pmull.h
/isa-l/crc/aarch64/crc_aarch64_dispatcher.c
/isa-l/crc/aarch64/crc_common_pmull.h
/isa-l/erasure_code/aarch64/ec_aarch64_dispatcher.c
/isa-l/erasure_code/aarch64/gf_2vect_dot_prod_neon.S
/isa-l/erasure_code/aarch64/gf_2vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_2vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_2vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_3vect_dot_prod_neon.S
/isa-l/erasure_code/aarch64/gf_3vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_3vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_3vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_4vect_dot_prod_neon.S
/isa-l/erasure_code/aarch64/gf_4vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_4vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_4vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_5vect_dot_prod_neon.S
/isa-l/erasure_code/aarch64/gf_5vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_5vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_5vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_6vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_6vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_6vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_7vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_8vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_vect_dot_prod_neon.S
/isa-l/erasure_code/aarch64/gf_vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_vect_mad_neon.S
/isa-l/erasure_code/aarch64/gf_vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_vect_mul_neon.S
/isa-l/erasure_code/aarch64/gf_vect_mul_sve.S
/isa-l/erasure_code/ec_base.c
/isa-l/erasure_code/ec_base_aliases.c
/isa-l/erasure_code/gf_vect_dot_prod_1tbl.c
/isa-l/erasure_code/gf_vect_mul_base_test.c
/isa-l/erasure_code/gf_vect_mul_test.c
/isa-l/erasure_code/ppc64le/gf_vect_mul_vsx.c
aarch64/encode_df.S
aarch64/gen_icf_map.S
aarch64/igzip_decode_huffman_code_block_aarch64.S
aarch64/igzip_deflate_body_aarch64.S
aarch64/igzip_deflate_finish_aarch64.S
aarch64/igzip_deflate_hash_aarch64.S
aarch64/igzip_isal_adler32_neon.S
aarch64/igzip_multibinary_aarch64_dispatcher.c
aarch64/igzip_set_long_icf_fg.S
aarch64/isal_deflate_icf_body_hash_hist.S
aarch64/isal_deflate_icf_finish_hash_hist.S
aarch64/isal_update_histogram.S
/isa-l/include/aarch64_label.h
/isa-l/include/aarch64_multibinary.h
/isa-l/include/gf_vect_mul.h
/isa-l/mem/aarch64/mem_aarch64_dispatcher.c
/isa-l/mem/aarch64/mem_zero_detect_neon.S
/isa-l/raid/aarch64/pq_check_neon.S
/isa-l/raid/aarch64/pq_gen_neon.S
/isa-l/raid/aarch64/raid_aarch64_dispatcher.c
/isa-l/raid/aarch64/xor_check_neon.S
/isa-l/raid/aarch64/xor_gen_neon.S
/isa-l/tools/check_format.sh
9c7e3b9f03-Aug-2022 Greg Tucker <greg.b.tucker@intel.com>

test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

test: Change perf tests to warm by default

The cold versions of tests depended on a fixed size of last level
cache that is too low on some arch and too high for the total
available memory on others.

Change-Id: Iee98403f9ace02e01b810c296a5fe44b933bfb17
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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9f75defd14-Jul-2022 Greg Tucker <greg.b.tucker@intel.com>

Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead

Remove all slver legacy segments

The relic slver is no longer used for individual versioning
on functions and is confusing tools looking for data in text
sections. This removes all instances instead of fixing since
its usefulness is waining. Fixes #221

Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>

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/isa-l/Makefile.nmake
/isa-l/crc/crc16_t10dif_01.asm
/isa-l/crc/crc16_t10dif_by4.asm
/isa-l/crc/crc16_t10dif_copy_by4.asm
/isa-l/crc/crc32_gzip_refl_by8.asm
/isa-l/crc/crc32_ieee_01.asm
/isa-l/crc/crc32_ieee_by4.asm
/isa-l/crc/crc32_iscsi_00.asm
/isa-l/crc/crc32_iscsi_01.asm
/isa-l/crc/crc64_base.c
/isa-l/crc/crc64_ecma_norm_by8.asm
/isa-l/crc/crc64_ecma_refl_by8.asm
/isa-l/crc/crc64_iso_norm_by8.asm
/isa-l/crc/crc64_iso_refl_by8.asm
/isa-l/crc/crc64_jones_norm_by8.asm
/isa-l/crc/crc64_jones_refl_by8.asm
/isa-l/crc/crc64_multibinary.asm
/isa-l/crc/crc_base.c
/isa-l/crc/crc_multibinary.asm
/isa-l/erasure_code/ec_base.c
/isa-l/erasure_code/ec_highlevel_func.c
/isa-l/erasure_code/ec_multibinary.asm
/isa-l/erasure_code/gf_2vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_2vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_2vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_2vect_mad_avx.asm
/isa-l/erasure_code/gf_2vect_mad_avx2.asm
/isa-l/erasure_code/gf_2vect_mad_sse.asm
/isa-l/erasure_code/gf_3vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_3vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_3vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_3vect_mad_avx.asm
/isa-l/erasure_code/gf_3vect_mad_avx2.asm
/isa-l/erasure_code/gf_3vect_mad_sse.asm
/isa-l/erasure_code/gf_4vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_4vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_4vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_4vect_mad_avx.asm
/isa-l/erasure_code/gf_4vect_mad_avx2.asm
/isa-l/erasure_code/gf_4vect_mad_sse.asm
/isa-l/erasure_code/gf_5vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_5vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_5vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_5vect_mad_avx.asm
/isa-l/erasure_code/gf_5vect_mad_avx2.asm
/isa-l/erasure_code/gf_5vect_mad_sse.asm
/isa-l/erasure_code/gf_6vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_6vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_6vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_6vect_mad_avx.asm
/isa-l/erasure_code/gf_6vect_mad_avx2.asm
/isa-l/erasure_code/gf_6vect_mad_sse.asm
/isa-l/erasure_code/gf_vect_dot_prod_avx.asm
/isa-l/erasure_code/gf_vect_dot_prod_avx2.asm
/isa-l/erasure_code/gf_vect_dot_prod_sse.asm
/isa-l/erasure_code/gf_vect_mad_avx.asm
/isa-l/erasure_code/gf_vect_mad_avx2.asm
/isa-l/erasure_code/gf_vect_mad_sse.asm
/isa-l/erasure_code/gf_vect_mul_avx.asm
/isa-l/erasure_code/gf_vect_mul_sse.asm
huff_codes.c
igzip.c
igzip_inflate.c
/isa-l/include/reg_sizes.asm
/isa-l/raid/pq_check_sse.asm
/isa-l/raid/pq_check_sse_i32.asm
/isa-l/raid/pq_gen_avx.asm
/isa-l/raid/pq_gen_avx2.asm
/isa-l/raid/pq_gen_sse.asm
/isa-l/raid/pq_gen_sse_i32.asm
/isa-l/raid/raid_base.c
/isa-l/raid/raid_multibinary.asm
/isa-l/raid/xor_check_sse.asm
/isa-l/raid/xor_gen_avx.asm
/isa-l/raid/xor_gen_sse.asm
/isa-l/tools/gen_nmake.mk
8b7c1b8020-Apr-2022 Martin Oliveira <martin.oliveira@eideticom.com>

igzip: fix neon adler32 load beyond buffer end

In the adler32_neon function, during the last iteration of the
loop through "accum32_neon", we would load data after the end of the
buffer (in the ld1

igzip: fix neon adler32 load beyond buffer end

In the adler32_neon function, during the last iteration of the
loop through "accum32_neon", we would load data after the end of the
buffer (in the ld1 instruction, the "start" register points to the end
of the buffer).

If this memory is unmapped, this would cause a segfault. If the memory
is mapped, the checksum would be correct because that value would
only be used in the next iteration, but this happens during the last
iteration.

To fix this, we can simply do the load before incrementing "start". And
while we're at it, we can load directly into d0_v/d1_v, saving a couple
of mov's.

Finally, the ld1 done during the function initialization can be removed
as the values aren't used for anything.

Change-Id: I4a0f2811adc523852ebe774da0a6fb1f5419192f
Signed-off-by: Martin Oliveira <martin.oliveira@eideticom.com>

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5b1a519f31-Mar-2022 ZhaiMo <zhaimo03@kuaishou.com>

change some logic in compress_icf_map_g

Change-Id: Ibb59058b6d826e03833c53839613e54c3d2003a8
Signed-off-by: ZhaiMo <zhaimo14@mails.ucas.ac.cn>

d3cfb2fb11-Nov-2021 Ilya Leoshkevich <iii@linux.ibm.com>

Fix s390 build

The goal of this patch is to make isa-l testsuite pass on s390 with
minimal changes to the library. The one and only reason isa-l does not
work on s390 at the moment is that s390 is b

Fix s390 build

The goal of this patch is to make isa-l testsuite pass on s390 with
minimal changes to the library. The one and only reason isa-l does not
work on s390 at the moment is that s390 is big-endian, and isa-l
assumes little-endian at a lot of places.

There are two flavors of this: loading/storing integers from/to
memory, and overlapping structs. Loads/stores are already helpfully
wrapped by unaligned.h header, so replace the functions there with
endianness-aware variants. Solve struct member overlap by reversing
their order on big-endian.

Also, fix a couple of usages of uninitialized memory in the testsuite
(found with MemorySanitizer).

Fixes s390x part of #188.

Change-Id: Iaf14a113bd266900192cc8b44212f8a47a8c7753
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>

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/isa-l/.github/workflows/ci.yml
/isa-l/Makefile.am
/isa-l/Makefile.nmake
/isa-l/README.md
/isa-l/erasure_code/aarch64/Makefile.am
/isa-l/erasure_code/aarch64/ec_aarch64_dispatcher.c
/isa-l/erasure_code/aarch64/ec_aarch64_highlevel_func.c
/isa-l/erasure_code/aarch64/gf_2vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_2vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_3vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_3vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_4vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_4vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_5vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_5vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_6vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_6vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_7vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_8vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_vect_dot_prod_sve.S
/isa-l/erasure_code/aarch64/gf_vect_mad_sve.S
/isa-l/erasure_code/aarch64/gf_vect_mul_sve.S
/isa-l/erasure_code/ec_base.c
bitbuf2.h
encode_df.h
generate_custom_hufftables.c
huff_codes.c
huff_codes.h
huffman.h
igzip.c
igzip_base.c
igzip_icf_base.c
igzip_icf_body.c
igzip_inflate.c
igzip_rand_test.c
proc_heap_base.c
/isa-l/include/unaligned.h
/isa-l/isa-l.rc
/isa-l/make.inc
/isa-l/mem/Makefile.am
/isa-l/mem/mem_multibinary.asm
/isa-l/mem/mem_zero_detect_avx2.asm
/isa-l/mem/mem_zero_detect_base.c
/isa-l/mem/mem_zero_detect_test.c
/isa-l/tests/fuzz/igzip_simple_round_trip_fuzz_test.c
/isa-l/tools/gen_nmake.mk
/isa-l/tools/nasm-cet-filter.sh
/isa-l/tools/nasm-filter.sh
/isa-l/tools/yasm-cet-filter.sh
/isa-l/tools/yasm-filter.sh
94ec602618-Aug-2021 Ruben Vorderman <r.h.p.vorderman@lumc.nl>

Create headers based on compression parameters.

Instead of using a constant as default zlib header, create the header on the fly. Both zlib
header bytes depend on the wbits and compression level use

Create headers based on compression parameters.

Instead of using a constant as default zlib header, create the header on the fly. Both zlib
header bytes depend on the wbits and compression level used.
Make sure that ISA-L compression level 0 is advertised as the fastest compression in
both the gzip header (setting xfl flag to 0x04) and the zlib header (as 0, fastest, other levels are 1, fast).

Change-Id: I1f30e4397a0f5fcf6df593c40178e7d6f6c05328
Signed-off-by: Ruben Vorderman <r.h.p.vorderman@lumc.nl>

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