History log of /isa-l/erasure_code/ (Results 1 – 25 of 79)
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07f8028719-Nov-2024 Cornu, Marcel D <marcel.d.cornu@intel.com>

erasure_code: fix unaligned free error in perf apps on windows

Signed-off-by: Cornu, Marcel D <marcel.d.cornu@intel.com>


/isa-l/.clang-format-ignore
/isa-l/.github/workflows/ci.yml
/isa-l/Makefile.nmake
erasure_code_perf.c
erasure_code_update_perf.c
/isa-l/examples/crc/crc_combine_example.c
/isa-l/examples/ec/ec_piggyback_example.c
/isa-l/examples/ec/ec_simple_example.c
/isa-l/igzip/aarch64/igzip_multibinary_aarch64_dispatcher.c
/isa-l/igzip/adler32_base.c
/isa-l/igzip/adler32_perf.c
/isa-l/igzip/bitbuf2.h
/isa-l/igzip/checksum32_funcs_test.c
/isa-l/igzip/checksum_test_ref.h
/isa-l/igzip/encode_df.c
/isa-l/igzip/encode_df.h
/isa-l/igzip/flatten_ll.c
/isa-l/igzip/flatten_ll.h
/isa-l/igzip/generate_custom_hufftables.c
/isa-l/igzip/generate_static_inflate.c
/isa-l/igzip/huff_codes.c
/isa-l/igzip/huff_codes.h
/isa-l/igzip/huffman.h
/isa-l/igzip/hufftables_c.c
/isa-l/igzip/igzip.c
/isa-l/igzip/igzip_base.c
/isa-l/igzip/igzip_base_aliases.c
/isa-l/igzip/igzip_build_hash_table_perf.c
/isa-l/igzip/igzip_checksums.h
/isa-l/igzip/igzip_example.c
/isa-l/igzip/igzip_file_perf.c
/isa-l/igzip/igzip_hist_perf.c
/isa-l/igzip/igzip_icf_base.c
/isa-l/igzip/igzip_icf_body.c
/isa-l/igzip/igzip_inflate.c
/isa-l/igzip/igzip_inflate_test.c
/isa-l/igzip/igzip_level_buf_structs.h
/isa-l/igzip/igzip_perf.c
/isa-l/igzip/igzip_rand_test.c
/isa-l/igzip/igzip_semi_dyn_file_perf.c
/isa-l/igzip/igzip_sync_flush_example.c
/isa-l/igzip/igzip_wrapper.h
/isa-l/igzip/igzip_wrapper_hdr_test.c
/isa-l/igzip/inflate_std_vects.h
/isa-l/igzip/proc_heap_base.c
/isa-l/igzip/repeated_char_result.h
/isa-l/igzip/static_inflate.h
/isa-l/include/aarch64_multibinary.h
/isa-l/include/crc.h
/isa-l/include/crc64.h
/isa-l/include/erasure_code.h
/isa-l/include/gf_vect_mul.h
/isa-l/include/igzip_lib.h
/isa-l/include/mem_routines.h
/isa-l/include/raid.h
/isa-l/include/test.h
/isa-l/include/unaligned.h
/isa-l/make.inc
/isa-l/mem/aarch64/mem_aarch64_dispatcher.c
/isa-l/mem/mem_zero_detect_base.c
/isa-l/mem/mem_zero_detect_base_aliases.c
/isa-l/mem/mem_zero_detect_perf.c
/isa-l/mem/mem_zero_detect_test.c
/isa-l/programs/Makefile.am
/isa-l/programs/igzip_cli.c
/isa-l/raid/aarch64/raid_aarch64_dispatcher.c
/isa-l/raid/pq_check_test.c
/isa-l/raid/pq_gen_perf.c
/isa-l/raid/pq_gen_test.c
/isa-l/raid/raid_base.c
/isa-l/raid/raid_base_aliases.c
/isa-l/raid/xor_check_test.c
/isa-l/raid/xor_example.c
/isa-l/raid/xor_gen_perf.c
/isa-l/raid/xor_gen_test.c
/isa-l/tests/fuzz/igzip_checked_inflate_fuzz_test.c
/isa-l/tests/fuzz/igzip_dump_inflate_corpus.c
/isa-l/tests/fuzz/igzip_fuzz_inflate.c
/isa-l/tests/fuzz/igzip_simple_inflate_fuzz_test.c
/isa-l/tests/fuzz/igzip_simple_round_trip_fuzz_test.c
/isa-l/tools/format.sh
/isa-l/tools/gen_nmake.mk
300260a419-Apr-2024 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: reformat using new code style

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>


/isa-l/.clang-format
/isa-l/.clang-format-ignore
/isa-l/.github/workflows/ci.yml
/isa-l/CONTRIBUTING.md
/isa-l/crc/aarch64/crc64_rocksoft.c
/isa-l/crc/aarch64/crc_aarch64_dispatcher.c
/isa-l/crc/crc16_t10dif_copy_perf.c
/isa-l/crc/crc16_t10dif_copy_test.c
/isa-l/crc/crc16_t10dif_op_perf.c
/isa-l/crc/crc16_t10dif_perf.c
/isa-l/crc/crc16_t10dif_test.c
/isa-l/crc/crc32_funcs_test.c
/isa-l/crc/crc32_gzip_refl_perf.c
/isa-l/crc/crc32_ieee_perf.c
/isa-l/crc/crc32_iscsi_perf.c
/isa-l/crc/crc64_base.c
/isa-l/crc/crc64_example.c
/isa-l/crc/crc64_funcs_perf.c
/isa-l/crc/crc64_funcs_test.c
/isa-l/crc/crc64_ref.h
/isa-l/crc/crc_base.c
/isa-l/crc/crc_base_aliases.c
/isa-l/crc/crc_ref.h
/isa-l/crc/crc_simple_test.c
aarch64/ec_aarch64_dispatcher.c
aarch64/ec_aarch64_highlevel_func.c
ec_base.c
ec_base.h
ec_base_aliases.c
ec_highlevel_func.c
erasure_code_base_perf.c
erasure_code_base_test.c
erasure_code_perf.c
erasure_code_test.c
erasure_code_update_perf.c
erasure_code_update_test.c
gen_rs_matrix_limits.c
gf_inverse_test.c
gf_vect_dot_prod_1tbl.c
gf_vect_dot_prod_base_test.c
gf_vect_dot_prod_perf.c
gf_vect_dot_prod_test.c
gf_vect_mad_test.c
gf_vect_mul_base_test.c
gf_vect_mul_perf.c
gf_vect_mul_test.c
ppc64le/ec_base_vsx.c
ppc64le/ec_base_vsx.h
ppc64le/gf_2vect_dot_prod_vsx.c
ppc64le/gf_2vect_mad_vsx.c
ppc64le/gf_3vect_dot_prod_vsx.c
ppc64le/gf_3vect_mad_vsx.c
ppc64le/gf_4vect_dot_prod_vsx.c
ppc64le/gf_4vect_mad_vsx.c
ppc64le/gf_5vect_dot_prod_vsx.c
ppc64le/gf_5vect_mad_vsx.c
ppc64le/gf_6vect_dot_prod_vsx.c
ppc64le/gf_6vect_mad_vsx.c
ppc64le/gf_vect_dot_prod_vsx.c
ppc64le/gf_vect_mad_vsx.c
ppc64le/gf_vect_mul_vsx.c
/isa-l/tools/check_format.sh
/isa-l/tools/format.sh
38279f5e08-Mar-2024 Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

Avoid using x18 register

Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>

1b1ee1e120-Jan-2024 Mattias Ellert <mattias.ellert@physics.uu.se>

erasure_code: fix wrong return type

erasure_code/ppc64le/gf_vect_mul_vsx.c: In function '_gf_vect_mul_base':
erasure_code/ppc64le/gf_vect_mul_vsx.c:14:16: error: 'return' with a value, in function r

erasure_code: fix wrong return type

erasure_code/ppc64le/gf_vect_mul_vsx.c: In function '_gf_vect_mul_base':
erasure_code/ppc64le/gf_vect_mul_vsx.c:14:16: error: 'return' with a value, in function returning void [-Wreturn-mismatch]
14 | return 0;
| ^
erasure_code/ppc64le/gf_vect_mul_vsx.c:6:13: note: declared here
6 | static void _gf_vect_mul_base(int len, unsigned char *a, unsigned char *src,
| ^~~~~~~~~~~~~~~~~

Signed-off-by: Mattias Ellert <mattias.ellert@physics.uu.se>

show more ...

e0fd782912-Jan-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: use internal gf_vect_mul_base for ppc64le encoding

gf_vect_mul_base is expected to work for all buffer sizes.
However, this function is checking for size alignment to 32 bytes,
to foll

erasure_code: use internal gf_vect_mul_base for ppc64le encoding

gf_vect_mul_base is expected to work for all buffer sizes.
However, this function is checking for size alignment to 32 bytes,
to follow the other gf_vect_mul implementations.
Therefore, another implementation for this function is included
inside ppc64le folder to be used by the encoding functions.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

b8d5633e12-Jan-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: check for size alignment on powerpc gf_vect_mul_vsx implementation

Follows the rest of the gf_vect_mul implementations for other architectures,
and checks for size alignment, stated in

erasure_code: check for size alignment on powerpc gf_vect_mul_vsx implementation

Follows the rest of the gf_vect_mul implementations for other architectures,
and checks for size alignment, stated in the documentation.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

91e7906f12-Jan-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: check for size on gf_vect_mul_sse/avx

gf_vect_mul requires length to be multiple of 32 bytes,
so this check is added in the SSE/AVX implementations.

Signed-off-by: Pablo de Lara <pabl

erasure_code: check for size on gf_vect_mul_sse/avx

gf_vect_mul requires length to be multiple of 32 bytes,
so this check is added in the SSE/AVX implementations.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

2759771510-Jan-2024 liuqinfei <lucas.liuqinfei@huawei.com>

gf_vect_mul_sve: fix error and enable unit tests for aarch64

Signed-off-by: liuqinfei <lucas.liuqinfei@huawei.com>

e0fffbe402-Jan-2024 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: disable unit tests temporarily for aarch64/ppc64le

Some aarch64 and ppc64le implementations of gf_vect_mul do not check
for invalid sizes, so the unit test checking for negative return

erasure_code: disable unit tests temporarily for aarch64/ppc64le

Some aarch64 and ppc64le implementations of gf_vect_mul do not check
for invalid sizes, so the unit test checking for negative return value
from this function is disabled temporarily on these architectures.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

455fdded15-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: add missing aarch64 and powerpc interface for ec_init_tables

ec_init_tables is now a multi-implementation function,
so it requires a dispatcher for all architectures.

Signed-off-by: P

erasure_code: add missing aarch64 and powerpc interface for ec_init_tables

ec_init_tables is now a multi-implementation function,
so it requires a dispatcher for all architectures.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

402bd4f718-Dec-2023 Tomasz Kantecki <tomasz.kantecki@intel.com>

erasure_code: various fixes for static code analysis issues

Signed-off-by: Tomasz Kantecki <tomasz.kantecki@intel.com>

a3e2604315-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: [test] fix memory leak

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

abd80d3c15-Dec-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

erasure_code: check for size in gf_Xvect_mad_avx512_gfni

Length of data was not checked in implementation with AVX512+GFNI,
at the start of the gf_Xvect_mad_avx512_gfni functions, resulting
in buffe

erasure_code: check for size in gf_Xvect_mad_avx512_gfni

Length of data was not checked in implementation with AVX512+GFNI,
at the start of the gf_Xvect_mad_avx512_gfni functions, resulting
in buffer overflow if length was less than 64 bytes.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

show more ...

561a419b14-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: fix modules using incorrect unsigned jump

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

a53a20ea13-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add AVX2 5vect mad with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

47ed284713-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add AVX2 4vect mad with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

22b7f33d13-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add AVX2 3vect mad with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

d22bb19808-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: optimize AVX2-GFNI single vector mad implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

a0a149d608-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add AVX2 2vect mad with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

0052080f08-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: optimize AVX2 GFNI 2 vector dot product

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

3f87141d07-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: optimize AVX2 GFNI single vector dot product

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

164d9ff106-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add 2 vector AVX2 dot product with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

307d737b05-Dec-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add 3 vector AVX2 dot product with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

2ca781df29-Nov-2023 Pablo de Lara <pablo.de.lara.guarch@intel.com>

lib: reduce verbosity by default in tests

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

5f23c03430-Nov-2023 Marcel Cornu <marcel.d.cornu@intel.com>

erasure_code: add initial AVX2 mad with GFNI implementation

Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>

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