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Revision tags: v24.07-rc2, v24.07-rc1, v24.03, v24.03-rc4, v24.03-rc3, v24.03-rc2, v24.03-rc1 |
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1dd3e5e2 |
| 13-Feb-2024 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: optimize IPv4/IPv6 address conversion
Enhanced the move instruction to detect and optimize the conversion between 128-bit numbers (IPv6 addresses) and 64-bit (upper or lower part of IPv6 a
pipeline: optimize IPv4/IPv6 address conversion
Enhanced the move instruction to detect and optimize the conversion between 128-bit numbers (IPv6 addresses) and 64-bit (upper or lower part of IPv6 addresses) or 32-bit numbers (IPv4 addresses).
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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2f8168ea |
| 13-Feb-2024 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: add instruction for IPv6 address upper half
Added new instruction called "movh" to read/write the upper half of an IPv6 address, i.e. bits 127-64 of a 128-bit field.
Signed-off-by: Cristi
pipeline: add instruction for IPv6 address upper half
Added new instruction called "movh" to read/write the upper half of an IPv6 address, i.e. bits 127-64 of a 128-bit field.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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c66dfe7a |
| 14-Feb-2024 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: remove limitation on number of input ports
Removed the requirement that the number of pipeline input ports be a power of 2, which is problematic for many real life use-cases. Also adding c
pipeline: remove limitation on number of input ports
Removed the requirement that the number of pipeline input ports be a power of 2, which is problematic for many real life use-cases. Also adding checks for the output port validity used for sending the current packet.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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Revision tags: v23.11, v23.11-rc4 |
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93998f3c |
| 15-Nov-2023 |
Tyler Retzlaff <roretzla@linux.microsoft.com> |
add extension keyword to GCC statement expressions
Add __extension__ keyword to gcc statement expression extensions. This is necessary for MSVC support.
Signed-off-by: Tyler Retzlaff <roretzla@linu
add extension keyword to GCC statement expressions
Add __extension__ keyword to gcc statement expression extensions. This is necessary for MSVC support.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
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5a9a6ee8 |
| 29-Nov-2023 |
Stephen Hemminger <stephen@networkplumber.org> |
pipeline: replace zero length array with flex array
Zero length arrays are GNU extension. Replace with standard flex array.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Reviewed-by
pipeline: replace zero length array with flex array
Zero length arrays are GNU extension. Replace with standard flex array.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Reviewed-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
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Revision tags: v23.11-rc3, v23.11-rc2, v23.11-rc1, v23.07, v23.07-rc4, v23.07-rc3, v23.07-rc2, v23.07-rc1 |
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7253e3d2 |
| 04-Apr-2023 |
Tyler Retzlaff <roretzla@linux.microsoft.com> |
bitops: move bit count functions
Move the following inline functions from rte_common.h to rte_bitops.h
rte_combine32ms1b rte_combine64ms1b rte_bsf32 rte_bsf32_safe rte_bsf64 rte_bsf64_s
bitops: move bit count functions
Move the following inline functions from rte_common.h to rte_bitops.h
rte_combine32ms1b rte_combine64ms1b rte_bsf32 rte_bsf32_safe rte_bsf64 rte_bsf64_safe rte_fls_u32 rte_fls_u64 rte_is_power_of_2 rte_align32pow2 rte_align32prevpow2 rte_align64pow2 rte_align64prevpow2 rte_log2_u32 rte_log2_u64
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Acked-by: Ferruh Yigit <ferruh.yigit@amd.com> Acked-by: Morten Brørup <mb@smartsharesystems.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
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Revision tags: v23.03, v23.03-rc4, v23.03-rc3, v23.03-rc2, v23.03-rc1 |
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5b65690e |
| 10-Feb-2023 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support conversion between big and small fields
While the small fields (size <= 64 bits) can be in either network byte order (header fields) or host byte order (meta-data fields), the big
pipeline: support conversion between big and small fields
While the small fields (size <= 64 bits) can be in either network byte order (header fields) or host byte order (meta-data fields), the big fields (size > 64 bits) are always expected to be in network byte order (big endian), both header and metadata fields.
Previously, a big field could be involved in an assignment only when both the destination and the source are big fields of exactly the same size. This restriction is now relaxed significantly: in case a big field is involved as either destination or source, the other field can now be either a big field (of the same or different size) or a small header field, so in either case both destination and source are in the network byte order.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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8ba342ce |
| 07-Feb-2023 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: add RSS
Add pipeline support for the Receive Side Scaling (RSS) hashing. While the pipeline already supports the stateless hashing schemes, the RSS scheme uses a key configured by the cont
pipeline: add RSS
Add pipeline support for the Receive Side Scaling (RSS) hashing. While the pipeline already supports the stateless hashing schemes, the RSS scheme uses a key configured by the control plane and preserved between successive RSS hash invocations.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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3d60499a |
| 01-Feb-2023 |
Harshad Narayane <harshad.suresh.narayane@intel.com> |
pipeline: increase instruction table size
The complex P4 programs requires more custom instructions, therefore we increase the pipeline instruction table size from 256 to 1024.
Signed-off-by: Harsh
pipeline: increase instruction table size
The complex P4 programs requires more custom instructions, therefore we increase the pipeline instruction table size from 256 to 1024.
Signed-off-by: Harshad Narayane <harshad.suresh.narayane@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com> Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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Revision tags: v22.11, v22.11-rc4, v22.11-rc3, v22.11-rc2, v22.11-rc1 |
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d4e95281 |
| 30-Aug-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: add table entry ID read instruction
Add the entry ID instruction that reads the entry ID of the latest table lookup operation from the pipeline into the meta-data. The entry ID is then use
pipeline: add table entry ID read instruction
Add the entry ID instruction that reads the entry ID of the latest table lookup operation from the pipeline into the meta-data. The entry ID is then used by the register and meter instructions as the index into the register or meter array.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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42605e56 |
| 30-Aug-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
table: add entry ID for regular tables
Add support for unique ID for each table entry. The entry ID is retrieved as part of the table lookup operation and is saved by the pipeline for later use.
Si
table: add entry ID for regular tables
Add support for unique ID for each table entry. The entry ID is retrieved as part of the table lookup operation and is saved by the pipeline for later use.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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fa7723b5 |
| 19-Aug-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: configure hash function for learner tables
Make the hash function configurable for the learner pipeline tables.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-o
pipeline: configure hash function for learner tables
Make the hash function configurable for the learner pipeline tables.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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9560a329 |
| 19-Aug-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: configure hash function for regular tables
Make the hash function configurable for the regular pipeline tables.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-o
pipeline: configure hash function for regular tables
Make the hash function configurable for the regular pipeline tables.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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9ebff617 |
| 12-Aug-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support moving large structure fields
Add support to the move instruction for operands bigger than 64 bits.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-b
pipeline: support moving large structure fields
Add support to the move instruction for operands bigger than 64 bits.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Harshad Narayane <harshad.suresh.narayane@intel.com>
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d69c90c8 |
| 28-Jul-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: add pipeline name
Add an unique name to every pipeline. This enables the library to maintain a list of the existing pipeline objects, which can be queried by the application.
Signed-off-b
pipeline: add pipeline name
Add an unique name to every pipeline. This enables the library to maintain a list of the existing pipeline objects, which can be queried by the application.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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Revision tags: v22.07, v22.07-rc4, v22.07-rc3, v22.07-rc2 |
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a1b2afe4 |
| 16-Jun-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: rework optimization pattern for header generation
The P4 language requires marking a header as valid before any of the header fields are written as opposed to after the writes are done. He
pipeline: rework optimization pattern for header generation
The P4 language requires marking a header as valid before any of the header fields are written as opposed to after the writes are done. Hence, the optimization of replacing the sequence of instructions to generate a header by reading it from the table action data with a single DMA internal instruction are reworked from "mov all + validate -> dma" to "validate + mov all -> dma".
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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Revision tags: v22.07-rc1 |
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92f2944d |
| 20-May-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support hash functions
Add support for hash functions that compute a signature for an array of bytes read from a packet header or meta-data. Useful for flow affinity-based load balancing.
pipeline: support hash functions
Add support for hash functions that compute a signature for an array of bytes read from a packet header or meta-data. Useful for flow affinity-based load balancing.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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e2ecc535 |
| 20-May-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: improve learner table timers
Enable the pipeline to use the improved learner table timer operation through the new "rearm" instruction.
Signed-off-by: Cristian Dumitrescu <cristian.dumitr
pipeline: improve learner table timers
Enable the pipeline to use the improved learner table timer operation through the new "rearm" instruction.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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8186c0bb |
| 20-May-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
table: improve learner table timers
Previously, on lookup hit, the hit key had its timer automatically rearmed with the same timeout in order to prevent its expiration. Now, a broader set of actions
table: improve learner table timers
Previously, on lookup hit, the hit key had its timer automatically rearmed with the same timeout in order to prevent its expiration. Now, a broader set of actions is available on lookup hit, which has to be managed explicitly: the key can have its timer rearmed with the same or with a different timeout, or the key timer can be left unmodified. The latter option allows the key to expire naturally when the timer eventually runs out, unless the key is hit again and its timer rearmed at that point. Needed by the TCP connection tracking state machine.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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5ec76d29 |
| 06-Apr-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support packet recirculation
Add support for packet recirculation. The current packet is flagged for recirculation using the new "recirculate" instruction; on TX, this flag causes the pack
pipeline: support packet recirculation
Add support for packet recirculation. The current packet is flagged for recirculation using the new "recirculate" instruction; on TX, this flag causes the packet to execute the full pipeline again as if it was a new packet, except the packet meta-data is preserved. The new "recircid" instruction can be used to read the pass number in case the packet goes several times through the pipeline.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
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dac0ecd9 |
| 06-Apr-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support packet mirroring
The packet mirroring is configured through slots and sessions, with the number of slots and sessions set at init.
The new "mirror" instruction assigns one of the
pipeline: support packet mirroring
The packet mirroring is configured through slots and sessions, with the number of slots and sessions set at init.
The new "mirror" instruction assigns one of the existing sessions to a specific slot, which results in scheduling a mirror operation for the current packet to be executed later at the time the packet is either transmitted or dropped.
Several copies of the same input packet can be mirrored to different output ports by using multiple slots.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Kamalakannan R <kamalakannan.r@intel.com>
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775be5b5 |
| 27-Apr-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: fix emit instruction for invalid headers
Fix the emit instruction for the pathological case of all headers to be emitted being invalid. In this case, the for loop was essentially skipped a
pipeline: fix emit instruction for invalid headers
Fix the emit instruction for the pathological case of all headers to be emitted being invalid. In this case, the for loop was essentially skipped and the last emitted header (or an invalid memory location) getting corrupted by setting its size to 0 through the assignment to ho->n_bytes right after the for loop.
Fixes: d60dbdc88a3e ("pipeline: create inline functions for emit instruction") Cc: stable@dpdk.org
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Venkata Suresh Kumar P <venkata.suresh.kumar.p@intel.com> Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>
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Revision tags: v22.03, v22.03-rc4, v22.03-rc3, v22.03-rc2, v22.03-rc1 |
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2a11b503 |
| 11-Feb-2022 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: support checksum for variable size headers
Added checksum support for variable size headers such as IPv4 headers with options.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@inte
pipeline: support checksum for variable size headers
Added checksum support for variable size headers such as IPv4 headers with options.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com> Signed-off-by: Harshad Narayane <harshad.suresh.narayane@intel.com>
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c07aaa65 |
| 27-Nov-2021 |
Cristian Dumitrescu <cristian.dumitrescu@intel.com> |
pipeline: improve drop instruction
The output port to be used as the drop port is now determined when the drop instruction is executed as opposed to being statically determined at instruction transl
pipeline: improve drop instruction
The output port to be used as the drop port is now determined when the drop instruction is executed as opposed to being statically determined at instruction translation time and hardcoded in the opcode.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>
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7be78d02 |
| 29-Nov-2021 |
Josh Soref <jsoref@gmail.com> |
fix spelling in comments and strings
The tool comes from https://github.com/jsoref
Signed-off-by: Josh Soref <jsoref@gmail.com> Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
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