common/mlx5: reduce HCA attribute type sizes

A number of `log_max_*` fields' types are unnecessarily large, and can
be reduced to `uint8_t`.

Signed-off-by: Igor Gutorov <igootorov@gmail.com>
Acked-

common/mlx5: reduce HCA attribute type sizes

A number of `log_max_*` fields' types are unnecessarily large, and can
be reduced to `uint8_t`.

Signed-off-by: Igor Gutorov <igootorov@gmail.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: fix reported Rx/Tx descriptor limits

Currently, `rte_eth_dev_info.rx_desc_lim.nb_max` as well as
`rte_eth_dev_info.tx_desc_lim.nb_max` shows 65535 as the limit,
which results in a few prob

net/mlx5: fix reported Rx/Tx descriptor limits

Currently, `rte_eth_dev_info.rx_desc_lim.nb_max` as well as
`rte_eth_dev_info.tx_desc_lim.nb_max` shows 65535 as the limit,
which results in a few problems:

* It is not the actual Rx/Tx queue limit
* Allocating an Rx queue and passing `rx_desc_lim.nb_max` results in an
integer overflow and 0 ring size:

```
rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool);
```

Which overflows ring size and generates the following log:
```
mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the
next power of two (0)
```
The same holds for allocating a Tx queue.

Fixes: e60fbd5b24fc ("mlx5: add device configure/start/stop")
Cc: stable@dpdk.org

Signed-off-by: Igor Gutorov <igootorov@gmail.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: add hardware queue object context dump

Add debug capability to mlx5 PMD to dump SQ/RQ/CQ HW object context for
a given port/queue. The context dump can provide some real-time
information o

net/mlx5: add hardware queue object context dump

Add debug capability to mlx5 PMD to dump SQ/RQ/CQ HW object context for
a given port/queue. The context dump can provide some real-time
information on cause of certain Tx/Rx Failures.

Signed-off-by: Kiran Vedere <kiranv@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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common/mlx5: read connection tracking attributes

Need to read maximum connection tracking
objects from HCA attributes.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowsk

common/mlx5: read connection tracking attributes

Need to read maximum connection tracking
objects from HCA attributes.

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>

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common/mlx5: query GENEVE TLV option parser

Add a new function to query information about GENEVE TLV option parser.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmi

common/mlx5: query GENEVE TLV option parser

Add a new function to query information about GENEVE TLV option parser.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add GENEVE option sample ID as attribute

This patch adds the GENEVE option sample ID into HCA attribute
structure.
This sample ID is used as the input of
"mlx5_devx_cmd_match_sample_inf

common/mlx5: add GENEVE option sample ID as attribute

This patch adds the GENEVE option sample ID into HCA attribute
structure.
This sample ID is used as the input of
"mlx5_devx_cmd_match_sample_info_query" function when flex parser
profile is 0.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add PRM attribute for TLV sample

Add GENEVE TLV sample fields in 2 places:
1. New HCA capabilities indicating GENEVE TLV sample is supported.
2. New fields in "mlx5_ifc_geneve_tlv_optio

common/mlx5: add PRM attribute for TLV sample

Add GENEVE TLV sample fields in 2 places:
1. New HCA capabilities indicating GENEVE TLV sample is supported.
2. New fields in "mlx5_ifc_geneve_tlv_option_bits" structure.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add GENEVE TLV option attribute structure

Add a new structure "mlx5_devx_geneve_tlv_option_attr" to use in GENEVE
TLV option creation.
Later this structure will be used by GENEVE TLV op

common/mlx5: add GENEVE TLV option attribute structure

Add a new structure "mlx5_devx_geneve_tlv_option_attr" to use in GENEVE
TLV option creation.
Later this structure will be used by GENEVE TLV option query operation
as well.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add system image GUID attribute

Add to the "system_image_guid" filed describing uniquely the physical
device into "mlx5_hca_attr" structure.

Signed-off-by: Michael Baum <michaelba@nvid

common/mlx5: add system image GUID attribute

Add to the "system_image_guid" filed describing uniquely the physical
device into "mlx5_hca_attr" structure.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: fix query sample info capability

Query sample info operation might be used by either Geneve TLV option or
parse graph. Each operations can be supported regardless to another
according t

common/mlx5: fix query sample info capability

Query sample info operation might be used by either Geneve TLV option or
parse graph. Each operations can be supported regardless to another
according the configured profile.

In current implementation, the query sample info capability is turn on
only when parse graph operation is supported adding unnecessary
requirement for Geneve TLV option.

This patch adds different cap for Geneve TLV option.

Fixes: bc0a9303ed6a ("net/mlx5: adopt new sample ID")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: update IPv6 traffic class modification

New PRM defined new field OUT_IPV6_TRAFFIC_CLASS for IPv6 which will be
used by both IPv6 ECN and DSCP. A new cap bit
modify_out_ipv6_traffic_class i

net/mlx5: update IPv6 traffic class modification

New PRM defined new field OUT_IPV6_TRAFFIC_CLASS for IPv6 which will be
used by both IPv6 ECN and DSCP. A new cap bit
modify_out_ipv6_traffic_class is added. It can be used to check if the
new field is supported by FW.

However, IPv6 ECN and DSCP starts from different offset in the same byte.
Update SWS and HWS to used the new field and introduce extra offset for
IPv6 DSCP data and mask to solve the issue.

Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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net/mlx5: support more HW registers

This commit adds the support for a additional registers that were added
to the HW.

Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnow

net/mlx5: support more HW registers

This commit adds the support for a additional registers that were added
to the HW.

Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: extend HCA attribute query for NSH

Add NSH supporting field in two places:
1. New HCA capability indicating NSH is supported
2. New field in "mlx5_ifc_per_protocol_networking_offload_ca

common/mlx5: extend HCA attribute query for NSH

Add NSH supporting field in two places:
1. New HCA capability indicating NSH is supported
2. New field in "mlx5_ifc_per_protocol_networking_offload_caps_bits"
structure

Signed-off-by: Haifei Luo <haifeil@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>

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common/mlx5: add WQE-based QP synchronous basics

Nvidia HW provides a synchronous mechanism between QPs. When
creating the QPs, user can set one as primary and another as
follower. The follower QP's

common/mlx5: add WQE-based QP synchronous basics

Nvidia HW provides a synchronous mechanism between QPs. When
creating the QPs, user can set one as primary and another as
follower. The follower QP's WQE execution can be controlled
by primary QP via SEND_EN WQE.

This commit introduces the SEND_EN WQE to improve the WQE
execution sync-up between primary and follower QPs.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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crypto/mlx5: add AES-GCM query and initialization

AES-GCM provides both authenticated encryption and the ability to check
the integrity and authentication of additional authenticated data (AAD)
that

crypto/mlx5: add AES-GCM query and initialization

AES-GCM provides both authenticated encryption and the ability to check
the integrity and authentication of additional authenticated data (AAD)
that is sent in the clear.

This commit adds the AES-GCM attributes query and initialization function.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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common/mlx5: query maximum modify pattern length

This patch adds querying the HCA capabilities for maximum supported
pattern length for Header Modify Pattern objects.

Signed-off-by: Dariusz Sosnows

common/mlx5: query maximum modify pattern length

This patch adds querying the HCA capabilities for maximum supported
pattern length for Header Modify Pattern objects.

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: support enhanced multi-packet write on Windows

Add support for enhanced multi-packet write on Windows.

Enhanced multi-packet write allows the Tx burst function to pack up
multiple packets

net/mlx5: support enhanced multi-packet write on Windows

Add support for enhanced multi-packet write on Windows.

Enhanced multi-packet write allows the Tx burst function to pack up
multiple packets in a single descriptor session to save PCI bandwidth
and improve performance.

The feature can be controlled by the txq_mpw_en PMD argument:

txq_mpw_en=1 - PMD will first attempt to use "enhanced multi packet write"
if the feature is not supported by the HW the legacy "multi packet write"
will be used.
if both are unsupported the multi packet write feature is disabled.

txq_mpw_en=0 - multi packet write is disabled.

txq_mpw_en unset(default) - enhanced multi packet write
will be activated if supported.
if unsupported the multi packet write feature is disabled.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Tested-by: Pier Damouny <pdamouny@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: support CQE compression on Windows

CQE Compression reduces PCI overhead by coalescing and compressing
multiple CQEs into a single merged CQE.

Add supported for the CQE compression feature

net/mlx5: support CQE compression on Windows

CQE Compression reduces PCI overhead by coalescing and compressing
multiple CQEs into a single merged CQE.

Add supported for the CQE compression feature on Windows.
feature is enabled by default unless not supported by the HW
or if the rxq_cqe_comp_en PMD argument is explicitly disabled.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Tested-by: Pier Damouny <pdamouny@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: support multi-packet Rx queue on Windows

Multi-Packet RQ can further save PCIe bandwidth by posting a single large
buffer for multiple packets.

Instead of posting a buffer per a packet, o

net/mlx5: support multi-packet Rx queue on Windows

Multi-Packet RQ can further save PCIe bandwidth by posting a single large
buffer for multiple packets.

Instead of posting a buffer per a packet, one large buffer is posted
to receive multiple packets on the buffer.

Add support for multi-packet RQ on Windows.
The feature is disabled by default and can by enabled
by setting mprq_en=1 in the PMD specific arguments.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Tested-by: Pier Damouny <pdamouny@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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net/mlx5: adopt new sample ID

Extended sample ID is the behavior of the current firmware and this
change was reverted.
In Apr GA, the sample ID will be the same as 22.11 DPDK (0-7).
Now, the sample

net/mlx5: adopt new sample ID

Extended sample ID is the behavior of the current firmware and this
change was reverted.
In Apr GA, the sample ID will be the same as 22.11 DPDK (0-7).
Now, the sample ID returned by mlx5_devx_cmd_query_parse_samples()
is still 0-7 and can be used directly by legacy SWS logic.

For HWS, the application should refer to the attributes returned by
mlx5_devx_cmd_query_match_sample_info to get the sample_dw_data/
modify_field_id/sample_dw_ok_bit/sample_dw_ok_bit_offset.

Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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common/mlx5: fix sample ID backward compatibility

The sample ID of parse graph should be treated as a single
value.
Add support for new query operation "QUERY_MATCH_SAMPLE_INFO".
This operation prov

common/mlx5: fix sample ID backward compatibility

The sample ID of parse graph should be treated as a single
value.
Add support for new query operation "QUERY_MATCH_SAMPLE_INFO".
This operation provides sample information for parse graph sample.
DevX commands are only available when dv_flow_en is not zero.

Fixes: f1324a171aac ("net/mlx5: adopt IPv6 routing extension PRM definition")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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common/mlx5: detect enhanced CQE compression capability

Enhanced CQE Compression is designed for better latency and SW utilization.
Check the HCA capabilities to see if Enhanced CQE Compression is s

common/mlx5: detect enhanced CQE compression capability

Enhanced CQE Compression is designed for better latency and SW utilization.
Check the HCA capabilities to see if Enhanced CQE Compression is supported.
Basic or Enhanced CQE Compression can be set as the CQE Compression Layout.
Enhanced CQE Compression can be selected only if it is supported by the FW.

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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net/mlx5: add LAG Rx port affinity in PRM

This patch adds function to query HCA capability via Devx for
lag_rx_port_affinity.

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ov

net/mlx5: add LAG Rx port affinity in PRM

This patch adds function to query HCA capability via Devx for
lag_rx_port_affinity.

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

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common/mlx5: check LZ4 capabilities

Add capabilities check for LZ4 decompression algorithm.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

compress/mlx5: support metadata layout added in BlueField-3

Commit [1] add support in BlueField-3, but BlueField-3 has different
GGA opaque structure than BlueField-2.

This patch updates the PRM st

compress/mlx5: support metadata layout added in BlueField-3

Commit [1] add support in BlueField-3, but BlueField-3 has different
GGA opaque structure than BlueField-2.

This patch updates the PRM structure to include both versions, and
calculate the relevant offset for each version in control path.

[1] Commit 559014f232b4 ("compress/mlx5: add Bluefield-3 device ID")

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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