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e7750639 |
| 10-Jan-2025 |
Andre Muezerie <andremue@linux.microsoft.com> |
drivers: replace packed attributes
MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro
drivers: replace packed attributes
MSVC struct packing is not compatible with GCC. Replace macro __rte_packed with __rte_packed_begin to push existing pack value and set packing to 1-byte and macro __rte_packed_end to restore the pack value prior to the push.
Macro __rte_packed_end is deliberately utilized to trigger a MSVC compiler warning if no existing packing has been pushed allowing easy identification of locations where the __rte_packed_begin is missing.
Signed-off-by: Andre Muezerie <andremue@linux.microsoft.com> Reviewed-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
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Revision tags: v24.11, v24.11-rc4, v24.11-rc3, v24.11-rc2 |
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90967539 |
| 12-Nov-2024 |
Shani Peretz <shperetz@nvidia.com> |
common/mlx5: fix misalignment
ASan reported a runtime error due to misalignment involving three structures.
The first issue arises when accessing l_inconst->cache[MLX5_LIST_GLOBAL]->h. If struct ml
common/mlx5: fix misalignment
ASan reported a runtime error due to misalignment involving three structures.
The first issue arises when accessing l_inconst->cache[MLX5_LIST_GLOBAL]->h. If struct mlx5_list_cache is not properly aligned, the pointer gc, assigned to l_inconst->cache[MLX5_LIST_GLOBAL], could be misaligned. To address this, the __rte_aligned(16) attribute was added to struct mlx5_list_inconst in struct mlx5_list, which includes struct mlx5_list_cache, ensuring that the entire mlx5_list structure, including mlx5_list_cache, is aligned to 64 bytes.
To resolve misalignment issues with struct mlx5_flow_handle, The initialization of resources for the ipool ensures that the ipool size is rounded up to the 8-byte boundary
The error in assigning values to actions[i] was due to potential padding or misalignment in struct mlx5_modification_cmd. To prevent such issues, the __rte_packed attribute was added to struct mlx5_modification_cmd, ensuring that the structure is packed without extra padding which helps avoid misaligned memory accesses.
Two performance degradation tests were conducted. Following are the results comparing this commit to the most recent commit in mlnx_dpdk_22.11 at that time (b69408ae453).
Before asan misalignment fix (average kflows/sec) - Insertion - 4461.269, Deletion - 7799.9992 After: Insertion - 4579.0642 , Deletion - 7913.0034
Fixes: 9a4c36880704 ("common/mlx5: optimize cache list object memory") Cc: stable@dpdk.org
Signed-off-by: Shani Peretz <shperetz@nvidia.com> Acked-by: Bing Zhao <bingz@nvidia.com>
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Revision tags: v24.11-rc1, v24.07, v24.07-rc4, v24.07-rc3, v24.07-rc2, v24.07-rc1 |
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e12a0166 |
| 14-May-2024 |
Tyler Retzlaff <roretzla@linux.microsoft.com> |
drivers: use stdatomic API
Replace the use of gcc builtin __atomic_xxx intrinsics with corresponding rte_atomic_xxx optional rte stdatomic API.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microso
drivers: use stdatomic API
Replace the use of gcc builtin __atomic_xxx intrinsics with corresponding rte_atomic_xxx optional rte stdatomic API.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Acked-by: Stephen Hemminger <stephen@networkplumber.org> Reviewed-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
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27595cd8 |
| 15-Apr-2024 |
Tyler Retzlaff <roretzla@linux.microsoft.com> |
drivers: move alignment attribute on types for MSVC
Move location of __rte_aligned(a) to new conventional location. The new placement between {struct,union} and the tag allows the desired alignment
drivers: move alignment attribute on types for MSVC
Move location of __rte_aligned(a) to new conventional location. The new placement between {struct,union} and the tag allows the desired alignment to be imparted on the type regardless of the toolchain being used for both C and C++. Additionally, it avoids confusion by Doxygen when generating documentation.
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> Acked-by: Morten Brørup <mb@smartsharesystems.com>
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Revision tags: v24.03, v24.03-rc4, v24.03-rc3, v24.03-rc2, v24.03-rc1, v23.11, v23.11-rc4, v23.11-rc3, v23.11-rc2, v23.11-rc1, v23.07, v23.07-rc4, v23.07-rc3, v23.07-rc2, v23.07-rc1, v23.03, v23.03-rc4, v23.03-rc3, v23.03-rc2, v23.03-rc1, v22.11, v22.11-rc4, v22.11-rc3, v22.11-rc2 |
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1094dd94 |
| 28-Oct-2022 |
David Marchand <david.marchand@redhat.com> |
cleanup compat header inclusions
With symbols going though experimental/stable stages, we accumulated a lot of discrepancies about inclusion of the rte_compat.h header.
Some headers are including i
cleanup compat header inclusions
With symbols going though experimental/stable stages, we accumulated a lot of discrepancies about inclusion of the rte_compat.h header.
Some headers are including it where unneeded, while others rely on implicit inclusion.
Fix unneeded inclusions: $ git grep -l include..rte_compat.h | xargs grep -LE '__rte_(internal|experimental)' | xargs sed -i -e '/#include..rte_compat.h/d'
Fix missing inclusion, by inserting rte_compat.h before the first inclusion of a DPDK header: $ git grep -lE '__rte_(internal|experimental)' | xargs grep -L include..rte_compat.h | xargs sed -i -e \ '0,/#include..\(rte_\|.*pmd.h.$\)/{ s/\(#include..\(rte_\|.*pmd.h.$\)\)/#include <rte_compat.h>\n\1/ }'
Fix missing inclusion, by inserting rte_compat.h after the last inclusion of a non DPDK header: $ for file in $(git grep -lE '__rte_(internal|experimental)' | xargs grep -L include..rte_compat.h); do tac $file > $file.$$ sed -i -e \ '0,/#include../{ s/\(#include..*$\)/#include <rte_compat.h>\n\n\1/ }' $file.$$ tac $file.$$ > $file rm $file.$$ done
Fix missing inclusion, by inserting rte_compat.h after the header guard: $ git grep -lE '__rte_(internal|experimental)' | xargs grep -L include..rte_compat.h | xargs sed -i -e \ '0,/#define/{ s/\(#define .*$\)/\1\n\n#include <rte_compat.h>/ }'
And finally, exclude rte_compat.h itself. $ git checkout lib/eal/include/rte_compat.h
At the end of all this, we have a clean tree: $ git grep -lE '__rte_(internal|experimental)' | xargs grep -L include..rte_compat.h buildtools/check-symbols.sh devtools/checkpatches.sh doc/guides/contributing/abi_policy.rst doc/guides/rel_notes/release_20_11.rst lib/eal/include/rte_compat.h
Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
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Revision tags: v22.11-rc1, v22.07, v22.07-rc4, v22.07-rc3, v22.07-rc2, v22.07-rc1, v22.03, v22.03-rc4, v22.03-rc3, v22.03-rc2, v22.03-rc1, v21.11, v21.11-rc4, v21.11-rc3, v21.11-rc2, v21.11-rc1, v21.08, v21.08-rc4, v21.08-rc3, v21.08-rc2 |
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ad435d32 |
| 21-Jul-2021 |
Xueming Li <xuemingl@nvidia.com> |
common/mlx5: add bus-agnostic layer
To support auxiliary bus, introduces common device driver and callbacks, supposed to replace mlx5 common PCI bus driver.
Mlx5 class drivers, i.e. eth, vDPA, rege
common/mlx5: add bus-agnostic layer
To support auxiliary bus, introduces common device driver and callbacks, supposed to replace mlx5 common PCI bus driver.
Mlx5 class drivers, i.e. eth, vDPA, regex and compress normally consumes single Verbs device context to probe a device. The Verbs device comes from PCI address if the device is PCI bus device, from Auxiliary sysfs if the device is auxiliary bus device. Currently only PCI bus is supported.
Common device driver is a middle layer between mlx5 class drivers and bus, resolve and abstract bus info to Verbs device for class drivers. Both PCI bus driver and Auxiliary bus driver can utilize the common driver layer to cast bus operations to mlx5 class drivers.
Legacy mlx5 common PCI bus driver still being used by mlx5 eth, vDPA, regex and compress PMD, will be removed once all PMD drivers migrate to new common driver.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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7e1cf892 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: support list non-lcore operations
This commit supports the list non-lcore operations with an extra sub-list and lock.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan
common/mlx5: support list non-lcore operations
This commit supports the list non-lcore operations with an extra sub-list and lock.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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9a4c3688 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: optimize cache list object memory
Currently, hash list uses the cache list as bucket list. The list in the buckets have the same name, ctx and callbacks. This wastes the memory.
This c
common/mlx5: optimize cache list object memory
Currently, hash list uses the cache list as bucket list. The list in the buckets have the same name, ctx and callbacks. This wastes the memory.
This commit abstracts all the name, ctx and callback members in the list to a constant struct and others to the inconstant struct, uses the wrapper functions to satisfy both hash list and cache list can set the list constant and inconstant struct individually.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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25481e50 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: allocate cache list memory individually
Currently, the list's local cache instance memory is allocated with the list. As the local cache instance array size is RTE_MAX_LCORE, most of th
common/mlx5: allocate cache list memory individually
Currently, the list's local cache instance memory is allocated with the list. As the local cache instance array size is RTE_MAX_LCORE, most of the cases the system will only have very limited cores. allocate the instance memory individually per core will be more economic to the memory.
This commit changes the instance array to pointer array, allocate the local cache memory only when the core is to be used.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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961b6774 |
| 13-Jul-2021 |
Matan Azrad <matan@nvidia.com> |
common/mlx5: add per-lcore cache to hash list utility
Using the mlx5 list utility object in the hlist buckets.
This patch moves the list utility object to the common utility, creates all the clone
common/mlx5: add per-lcore cache to hash list utility
Using the mlx5 list utility object in the hlist buckets.
This patch moves the list utility object to the common utility, creates all the clone operations for all the hlist instances in the driver.
Also adjust all the utility callbacks to be generic for both list and hlist.
Signed-off-by: Matan Azrad <matan@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com>
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6507c9f5 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: call list callbacks with context
This commit optimizes to call the list callback functions with global context directly.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Ma
common/mlx5: call list callbacks with context
This commit optimizes to call the list callback functions with global context directly.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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d03b7860 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: add per-lcore sharing flag in object list
Without lcores_share flag, mlx5 PMD was sharing the rdma-core objects between all lcores.
Having lcores_share flag disabled, means each lcore
common/mlx5: add per-lcore sharing flag in object list
Without lcores_share flag, mlx5 PMD was sharing the rdma-core objects between all lcores.
Having lcores_share flag disabled, means each lcore will have its own objects, which will eventually lead to increased insertion/deletion rates.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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9c373c52 |
| 13-Jul-2021 |
Suanming Mou <suanmingm@nvidia.com> |
common/mlx5: move list utility from net driver
Hash list is planned to be implemented with the cache list code.
This commit moves the list utility to common directory.
Signed-off-by: Suanming Mou
common/mlx5: move list utility from net driver
Hash list is planned to be implemented with the cache list code.
This commit moves the list utility to common directory.
Signed-off-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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Revision tags: v21.08-rc1, v21.05, v21.05-rc4, v21.05-rc3, v21.05-rc2 |
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25245d5d |
| 04-May-2021 |
Shiri Kuzin <shirik@nvidia.com> |
common/mlx5: share hash list tool
In order to use the hash list defined in net in other drivers, the hash list is moved to common utilities.
In addition, the log definition was moved from the commo
common/mlx5: share hash list tool
In order to use the hash list defined in net in other drivers, the hash list is moved to common utilities.
In addition, the log definition was moved from the common utilities to a dedicated new log file in common in order to prevent a conflict.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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Revision tags: v21.05-rc1 |
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2d2546ad |
| 15-Mar-2021 |
Asaf Penso <asafp@nvidia.com> |
common/mlx5: align log prefix across drivers
Some mlx5 PMDs define the log prefix as "mlx5_pmd" while others as "pmd_mlx5". The patch aligns all pmds to use the "mlx5_pmd" format.
Signed-off-by: As
common/mlx5: align log prefix across drivers
Some mlx5 PMDs define the log prefix as "mlx5_pmd" while others as "pmd_mlx5". The patch aligns all pmds to use the "mlx5_pmd" format.
Signed-off-by: Asaf Penso <asafp@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
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Revision tags: v21.02, v21.02-rc4, v21.02-rc3, v21.02-rc2, v21.02-rc1, v20.11, v20.11-rc5, v20.11-rc4, v20.11-rc3, v20.11-rc2, v20.11-rc1, v20.08, v20.08-rc4, v20.08-rc3, v20.08-rc2, v20.08-rc1, v20.05, v20.05-rc4, v20.05-rc3, v20.05-rc2, v20.05-rc1, v20.02, v20.02-rc4, v20.02-rc3, v20.02-rc2 |
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7b4f1e6b |
| 29-Jan-2020 |
Matan Azrad <matan@mellanox.com> |
common/mlx5: introduce common library
A new Mellanox vdpa PMD will be added to support vdpa operations by Mellanox adapters.
This vdpa PMD design includes mlx5_glue and mlx5_devx operations and lar
common/mlx5: introduce common library
A new Mellanox vdpa PMD will be added to support vdpa operations by Mellanox adapters.
This vdpa PMD design includes mlx5_glue and mlx5_devx operations and large parts of them are shared with the net/mlx5 PMD.
Create a new common library in drivers/common for mlx5 PMDs. Move mlx5_glue, mlx5_devx_cmds and their dependencies to the new mlx5 common library in drivers/common.
The files mlx5_devx_cmds.c, mlx5_devx_cmds.h, mlx5_glue.c, mlx5_glue.h and mlx5_prm.h are moved as is from drivers/net/mlx5 to drivers/common/mlx5.
Share the log mechanism macros. Separate also the log mechanism to allow different log level control to the common library.
Build files and version files are adjusted accordingly. Include lines are adjusted accordingly.
Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
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