| f0e79919 | 21-Dec-2016 |
Matthew Dillon <dillon@apollo.backplane.com> |
ahci - Add workarounds for Marvell 88SE9215
* This Marvell chip also needs some quirks. Probably most of the older Marvell chips need the same quirks, and the newer probably needs the FR cyclin
ahci - Add workarounds for Marvell 88SE9215
* This Marvell chip also needs some quirks. Probably most of the older Marvell chips need the same quirks, and the newer probably needs the FR cycling quirk, but for now I'm adding them only specifically as they are tested.
Reported-by: Edward Berger
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| 46d04d11 | 21-Dec-2016 |
Matthew Dillon <dillon@apollo.backplane.com> |
ahci - Improve port-multiplier detection
* Improve port-multiplier detaction by adding workarounds for poorly-implemented AHCI and PM chipsets. Now detects the popular Rosewill 4-bay enclosure,
ahci - Improve port-multiplier detection
* Improve port-multiplier detaction by adding workarounds for poorly-implemented AHCI and PM chipsets. Now detects the popular Rosewill 4-bay enclosure, which uses chipid 0x575f197b.
Increase device detect timeout from 3/10 second to 2 seconds. This enclosure stupidly takes extra time on the first COMRESET after a cold power-on to detect, I'm guessing because it is testing both its USB and its eSATA port.
This port multiplier sometimes returns ready before its software has completely initialized, causing PM register READs to succeed, but return data values of 0. If we get a data value of 0 for the REV register we sleep a little and try once more.
* Marvell AHCI chip does not immediately latch the signature on the second FIS during a software reset. Give it 500ms to do so.
Ignore a BSY condition between the first and second FIS during a software reset probe of the PM.
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| 8119d5f5 | 19-Dec-2016 |
Matthew Dillon <dillon@apollo.backplane.com> |
ahci - Implement FBS for port-multipliers
* Implement FBS (FIS-Based Switching) for port-multipliers. If the chipset supports it, the ahci driver now turns on FBS mode which allows us to queue
ahci - Implement FBS for port-multipliers
* Implement FBS (FIS-Based Switching) for port-multipliers. If the chipset supports it, the ahci driver now turns on FBS mode which allows us to queue concurrent requests to different targets.
Most AHCI chipsets do not support FBS resulting in poor port-multiplier performance.
- FBS is enabled in the PM probe.
- FBS must be disabled when doing a hard reset.
- In FBS mode commands must be queued to PREG_CI one at a time, and the target must be written to AHCI_PREG_FBS prior to activation via CI.
- RFIS area is larger, and RFIS responses are copied from the appropriate target index instead of index 0.
- Issue a COMRESET during the PM probe if a BSY status is recognized, which helps on chipsets which do not implement the SCLO cap.
* Clean-up a little logic in ahci_port_stop().
* Use the saved sc_cap to check for the SCLO capability instead of re-reading AHCI_REG_CAP in a few places.
* Dump the RFIS data to the console on error.
* Fixup sc_cap to directly incorporate quirks.
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| eb9f4c83 | 19-Dec-2016 |
Matthew Dillon <dillon@apollo.backplane.com> |
ahci - Add quirks for Marvell devices
* Add some quirks for badly broken Marvell devices.
* 88SE9172 - This badly broken AHCI chipset does not support FR *or* CR responses.
* 88SE9230 - This
ahci - Add quirks for Marvell devices
* Add some quirks for badly broken Marvell devices.
* 88SE9172 - This badly broken AHCI chipset does not support FR *or* CR responses.
* 88SE9230 - This badly broken AHCI chipset supports FR and CR, but cannot maintain FR across a disconnect. FRE must be cycled on the insertion detect in order to re-assert FR and be able to detect the new device.
This chipset also seems to have other problems, sometimes generating an error (TFES error) on SET_FEATURES, which does not happen when the drive is connected to the Intel AHCI chipset.
* Implement quirks for these devices. Also, don't enable FRE with POD and SUD (do it separately), and sequence CMD_ICC_ACTIVE a bit differently than before.
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| d90e4fd1 | 02-Aug-2015 |
Imre Vadász <imre@vdsz.com> |
ahci: Add some DevSleep defintions. Recognize DevSleep link state.
* Add the AHCI_PREG_SSTS_IPM_DEVSLEEP definition, and recognize the DevSleep power-state via the dev.ahci.X.Y.link_pwr_state sysc
ahci: Add some DevSleep defintions. Recognize DevSleep link state.
* Add the AHCI_PREG_SSTS_IPM_DEVSLEEP definition, and recognize the DevSleep power-state via the dev.ahci.X.Y.link_pwr_state sysctl.
* Use AHCI_PREG_SSTS_* definitions in ahci_port_link_pwr_state(), instead of SATA_PM_SSTS_* ones.
* Add CAP2 bits for DevSleep.
* Add DEVSLP register definitions.
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