| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| H A D | amdgpu_dc_debug.c | 146 plane_state->tiling_info.gfx8.num_banks, in pre_surface_trace()
147 plane_state->tiling_info.gfx8.bank_width, in pre_surface_trace()
148 plane_state->tiling_info.gfx8.bank_width_c, in pre_surface_trace()
149 plane_state->tiling_info.gfx8.bank_height, in pre_surface_trace()
150 plane_state->tiling_info.gfx8.bank_height_c, in pre_surface_trace()
151 plane_state->tiling_info.gfx8.tile_aspect, in pre_surface_trace()
152 plane_state->tiling_info.gfx8.tile_aspect_c, in pre_surface_trace()
153 plane_state->tiling_info.gfx8.tile_split, in pre_surface_trace()
154 plane_state->tiling_info.gfx8.tile_split_c, in pre_surface_trace()
155 plane_state->tiling_info.gfx8.tile_mode, in pre_surface_trace()
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| H A D | amdgpu_dc.c | 1562 if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, in get_plane_info_update_type()
1570 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
1863 surface->tiling_info = in copy_surface_update_to_plane()
1864 srf_update->plane_info->tiling_info; in copy_surface_update_to_plane()
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| H A D | amdgpu_dc_resource.c | 2118 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_mem_input.c | 106 union dc_tiling_info *tiling_info) in get_mi_tiling() argument
108 switch (tiling_info->gfx8.array_mode) { in get_mi_tiling()
141 union dc_tiling_info *tiling_info, in dce_mi_program_pte_vm() argument
146 enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info); in dce_mi_program_pte_vm()
512 union dc_tiling_info *tiling_info, in dce_mi_program_surface_config() argument
521 program_tiling(dce_mi, tiling_info); in dce_mi_program_surface_config()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | amdgpu_dce110_mem_input_v.c | 532 union dc_tiling_info *tiling_info, in get_dvmm_hw_setting() argument
550 switch (tiling_info->gfx8.array_mode) { in get_dvmm_hw_setting()
572 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_pte_vm() argument
576 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false); in dce_mem_input_v_program_pte_vm()
577 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true); in dce_mem_input_v_program_pte_vm()
645 union dc_tiling_info *tiling_info, in dce_mem_input_v_program_surface_config() argument
654 program_tiling(mem_input110, tiling_info, format); in dce_mem_input_v_program_surface_config()
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| H A D | amdgpu_dce110_hw_sequencer.c | 1837 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) in should_enable_fbc()
2506 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
2518 &plane_state->tiling_info, in dce110_program_front_end_for_pipe()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| H A D | mem_input.h | 142 union dc_tiling_info *tiling_info,
156 union dc_tiling_info *tiling_info,
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| H A D | hubp.h | 120 union dc_tiling_info *tiling_info,
134 union dc_tiling_info *tiling_info,
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm.c | 3146 const union dc_tiling_info *tiling_info, in fill_plane_dcc_attributes() argument
3173 input.swizzle_mode = tiling_info->gfx9.swizzle; in fill_plane_dcc_attributes()
3207 union dc_tiling_info *tiling_info, in fill_plane_buffer_attributes() argument
3215 memset(tiling_info, 0, sizeof(*tiling_info)); in fill_plane_buffer_attributes()
3272 tiling_info->gfx8.num_banks = num_banks; in fill_plane_buffer_attributes()
3273 tiling_info->gfx8.array_mode = in fill_plane_buffer_attributes()
3275 tiling_info->gfx8.tile_split = tile_split; in fill_plane_buffer_attributes()
3276 tiling_info->gfx8.bank_width = bankw; in fill_plane_buffer_attributes()
3277 tiling_info->gfx8.bank_height = bankh; in fill_plane_buffer_attributes()
3278 tiling_info->gfx8.tile_aspect = mtaspect; in fill_plane_buffer_attributes()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | dc.h | 748 union dc_tiling_info tiling_info; member
796 union dc_tiling_info tiling_info; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gem.c | 489 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
499 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); in amdgpu_gem_metadata_ioctl()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hubp.h | 296 union dc_tiling_info *tiling_info,
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| H A D | amdgpu_dcn20_hubp.c | 524 union dc_tiling_info *tiling_info, in hubp2_program_surface_config() argument
534 hubp2_program_tiling(hubp2, tiling_info, format); in hubp2_program_surface_config()
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| H A D | amdgpu_dcn20_resource.c | 2163 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
2164 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
3049 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn20_get_default_swizzle_mode()
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| H A D | amdgpu_dcn20_hwseq.c | 1450 &plane_state->tiling_info, in dcn20_update_dchubp_dpp()
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| /netbsd-src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| H A D | amdgpu_drm.h | 370 __u64 tiling_info; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_hubp.c | 531 union dc_tiling_info *tiling_info, in hubp1_program_surface_config() argument
539 hubp1_program_tiling(hubp, tiling_info, format); in hubp1_program_surface_config()
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| H A D | dcn10_hubp.h | 694 union dc_tiling_info *tiling_info,
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| H A D | amdgpu_dcn10_resource.c | 1255 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_get_default_swizzle_mode()
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| H A D | amdgpu_dcn10_hw_sequencer.c | 2347 &plane_state->tiling_info, in dcn10_update_dchubp_dpp()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| H A D | amdgpu_dcn_calcs.c | 336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
345 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
984 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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