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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td290 def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
291 (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
294 def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
295 (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>;
408 def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
409 (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
410 def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
411 (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
412 def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
413 (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
20 IntRegsLow8:$src3),
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
39 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
40 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
42 HvxVR:$src3),
43 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsicsV60.td171 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
172 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
175 IntRegs:$src3),
176 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
180 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
181 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
184 IntRegs:$src3),
185 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>;
189 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3),
190 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>;
[all …]
H A DHexagonIntrinsics.td145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
207 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
208 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
212 HvxVR:$src3),
213 (MI HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>,
310 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
311 (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>,
315 u3_0ImmPred:$src3),
317 u3_0ImmPred:$src3)>,
[all …]
H A DHexagonIntrinsicsV5.td178 u2_0ImmPred:$src3),
179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrXOP.td172 (ins VR128:$src1, VR128:$src2, VR128:$src3),
174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
176 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V,
179 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
184 VR128:$src3))]>, XOP_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
218 (v8i16 VR128:$src3))),
219 (VPMACSWWrr VR128:$src1, VR128:$src2, VR128:$src3)>;
221 (v4i32 VR128:$src3))),
222 (VPMACSDDrr VR128:$src1, VR128:$src2, VR128:$src3)>;
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (MemFrag addr:$src3))))]>,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td55 opaquemem:$src3), []>;
57 GR16:$src2, opaquemem:$src3,
81 (ins TILE:$src1, TILE:$src2, TILE:$src3),
82 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
85 (ins TILE:$src1, TILE:$src2, TILE:$src3),
86 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
89 (ins TILE:$src1, TILE:$src2, TILE:$src3),
90 "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
93 (ins TILE:$src1, TILE:$src2, TILE:$src3),
94 "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
[all …]
H A DX86InstrFragmentsSIMD.td204 def X86any_cmpp : PatFrags<(ops node:$src1, node:$src2, node:$src3),
205 [(X86strict_cmpp node:$src1, node:$src2, node:$src3),
206 (X86cmpp node:$src1, node:$src2, node:$src3)]>;
223 def X86any_cmpm : PatFrags<(ops node:$src1, node:$src2, node:$src3),
224 [(X86strict_cmpm node:$src1, node:$src2, node:$src3),
225 (X86cmpm node:$src1, node:$src2, node:$src3)]>;
541 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
542 [(X86strict_Fnmadd node:$src1, node:$src2, node:$src3),
543 (X86Fnmadd node:$src1, node:$src2, node:$src3)]>;
546 def X86any_Fmsub : PatFrags<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrSSE.td2021 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2023 (i8 timm:$src3))))], d>,
2027 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2029 (i8 timm:$src3))))], d>,
2035 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2039 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2043 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2047 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2053 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2056 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrAVX512.td529 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
531 "$src3, $src2, $src1", "$src1, $src2, $src3",
532 (vinsert_insert:$src3 (To.VT To.RC:$src1),
535 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
541 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
543 "$src3, $src2, $src1", "$src1, $src2, $src3",
544 (vinsert_insert:$src3 (To.VT To.RC:$src1),
547 (vinsert_for_mask:$src3 (To.VT To.RC:$src1),
798 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
799 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[all …]
H A DX86InstrShiftRotate.td696 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
697 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
699 (i8 imm:$src3)))]>,
703 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
704 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
706 (i8 imm:$src3)))]>,
710 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
711 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
713 (i8 imm:$src3)))]>,
717 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
[all …]
H A DX86InstrMMX.td111 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
116 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
119 (i8 timm:$src3)))]>,
526 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
527 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
529 GR32orGR64:$src2, timm:$src3))]>,
534 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/libhsail-rt/rt/
H A Dbitstring.c71 uint32_t src3) in __hsail_bitinsert_u32() argument
73 BITINSERT (uint32_t, src0, src1, src2, src3); in __hsail_bitinsert_u32()
78 uint32_t src3) in __hsail_bitinsert_u64() argument
80 BITINSERT (uint64_t, src0, src1, src2, src3); in __hsail_bitinsert_u64()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
36 : EXPCommon<done, "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")
100 (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
103 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
H A DSIInstrFormats.td361 bits<8> src3;
372 let Inst{63-56} = src3;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td672 def z_muladd : PatFrag<(ops node:$src1, node:$src2, node:$src3),
673 (add (mul node:$src1, node:$src2), node:$src3)>;
702 def any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
703 (any_fma node:$src1, node:$src2, (fneg node:$src3))>;
707 def z_any_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
708 (any_fma node:$src2, node:$src3, node:$src1)>;
709 def z_any_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
710 (any_fma node:$src2, node:$src3, (fneg node:$src1))>;
713 def any_fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
714 (fneg (any_fma node:$src1, node:$src2, node:$src3))>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/docs/AMDGPU/
H A Dgfx9_src_exp.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx10_src_exp.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx7_src_exp.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
H A Dgfx8_src_exp.rst18 * src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td469 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
470 "crc32 $dst, $src2, $src3",
473 GRRegs:$src3))]>;
512 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
513 "ladd $dst2, $dst1, $src1, $src2, $src3",
517 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
518 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
521 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
522 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt256 v ← bfp_MULTIPLY_ADD(src1, src3, src2)
261 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
266 v ← bfp_MULTIPLY_ADD(src1,src3,src2)
271 v ← bfp_MULTIPLY_ADD(src1, src3, bfp_NEGATE(src2))
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrNEON.td1196 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1199 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> {
1234 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1237 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1270 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1273 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1312 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1315 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1974 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1975 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dr8a7745-iwg22d-sodimm.dts292 playback = <&ssi3>, <&src3>, <&dvc0>;

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