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Searched refs:src2 (Results 1 – 25 of 330) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
24 def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
26 def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),
27 (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
28 def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),
29 (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/c6x/
H A Dc6x_intrinsics.h58 _sadd (int src1, int src2) in _sadd() argument
60 return __builtin_c6x_sadd (src1, src2); in _sadd()
64 _ssub (int src1, int src2) in _ssub() argument
66 return __builtin_c6x_ssub (src1, src2); in _ssub()
70 _add2 (int src1, int src2) in _add2() argument
72 return (int)__builtin_c6x_add2 ((__v2hi)src1, (__v2hi)src2); in _add2()
76 _sub2 (int src1, int src2) in _sub2() argument
78 return (int)__builtin_c6x_sub2 ((__v2hi)src1, (__v2hi)src2); in _sub2()
82 _add4 (int src1, int src2) in _add4() argument
84 return (int)__builtin_c6x_add4 ((__uv4qi)src1, (__uv4qi)src2); in _add4()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/c6x/
H A Dc6x_intrinsics.h58 _sadd (int src1, int src2) in _sadd() argument
60 return __builtin_c6x_sadd (src1, src2); in _sadd()
64 _ssub (int src1, int src2) in _ssub() argument
66 return __builtin_c6x_ssub (src1, src2); in _ssub()
70 _add2 (int src1, int src2) in _add2() argument
72 return (int)__builtin_c6x_add2 ((__v2hi)src1, (__v2hi)src2); in _add2()
76 _sub2 (int src1, int src2) in _sub2() argument
78 return (int)__builtin_c6x_sub2 ((__v2hi)src1, (__v2hi)src2); in _sub2()
82 _add4 (int src1, int src2) in _add4() argument
84 return (int)__builtin_c6x_add4 ((__uv4qi)src1, (__uv4qi)src2); in _add4()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
107 (vt128 (load addr:$src2)))))]>,
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
114 (vt128 VR128:$src2))))]>,
119 (ins VR128:$src1, VR128:$src2),
[all …]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
36 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td54 GR16:$src2,
57 GR16:$src2, opaquemem:$src3,
60 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
62 GR16:$src1, GR16:$src2))]>;
67 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
69 sibmem:$src2), []>;
81 (ins TILE:$src1, TILE:$src2, TILE:$src3),
82 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
85 (ins TILE:$src1, TILE:$src2, TILE:$src3),
86 "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
[all …]
H A DX86InstrShiftRotate.td34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
39 "shl{w}\t{$src2, $dst|$dst, $src2}",
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>,
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>,
47 (ins GR64:$src1, u8imm:$src2),
[all …]
H A DX86InstrCMovSetCC.td20 : I<0x40, MRMSrcRegCC, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, ccode:$cond),
21 "cmov${cond}{w}\t{$src2, $dst|$dst, $src2}",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
26 : I<0x40, MRMSrcRegCC, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, ccode:$cond),
27 "cmov${cond}{l}\t{$src2, $dst|$dst, $src2}",
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
32 :RI<0x40, MRMSrcRegCC, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, ccode:$cond),
33 "cmov${cond}{q}\t{$src2, $dst|$dst, $src2}",
35 (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
41 : I<0x40, MRMSrcMemCC, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2, ccode:$cond),
[all …]
H A DX86InstrKL.td21 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
22 "loadiwkey\t{$src2, $src1|$src1, $src2}",
23 [(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
41 def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
42 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
44 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
47 def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
48 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
50 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
53 def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
[all …]
H A DX86InstrCompiler.td675 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
677 "{$src2, $dst|$dst, $src2}"),
678 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
682 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
684 "{$src2, $dst|$dst, $src2}"),
685 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
690 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
692 "{$src2, $dst|$dst, $src2}"),
693 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
698 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
[all …]
H A DX86InstrArithmetic.td154 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
155 "imul{w}\t{$src2, $dst|$dst, $src2}",
157 (X86smul_flag GR16:$src1, GR16:$src2))]>,
159 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
160 "imul{l}\t{$src2, $dst|$dst, $src2}",
162 (X86smul_flag GR32:$src1, GR32:$src2))]>,
165 (ins GR64:$src1, GR64:$src2),
166 "imul{q}\t{$src2, $dst|$dst, $src2}",
168 (X86smul_flag GR64:$src1, GR64:$src2))]>,
174 (ins GR16:$src1, i16mem:$src2),
[all …]
H A DX86InstrAVX512.td174 def vselect_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
175 (vselect node:$mask, node:$src1, node:$src2), [{
179 def X86selects_mask : PatFrag<(ops node:$mask, node:$src1, node:$src2),
180 (X86selects node:$mask, node:$src1, node:$src2), [{
529 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
531 "$src3, $src2, $src1", "$src1, $src2, $src3",
533 (From.VT From.RC:$src2),
536 (From.VT From.RC:$src2),
541 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
543 "$src3, $src2, $src1", "$src1, $src2, $src3",
[all …]
H A DX86InstrMMX.td38 (ins VR64:$src1, VR64:$src2),
39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
40 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
45 (ins VR64:$src1, OType:$src2),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
56 (ins VR64:$src1, VR64:$src2),
57 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
58 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
61 (ins VR64:$src1, i64mem:$src2),
[all …]
/netbsd-src/sys/external/bsd/sljit/dist/sljit_src/
H A DsljitNativePPC_32.c47 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
55 if (dst != src2) in emit_single_op()
56 return push_inst(compiler, OR | S(src2) | A(dst) | B(src2)); in emit_single_op()
64 return push_inst(compiler, EXTSB | S(src2) | A(dst)); in emit_single_op()
65 return push_inst(compiler, INS_CLEAR_LEFT(dst, src2, 24)); in emit_single_op()
68 return push_inst(compiler, EXTSB | S(src2) | A(dst)); in emit_single_op()
70 SLJIT_ASSERT(dst == src2); in emit_single_op()
79 return push_inst(compiler, EXTSH | S(src2) | A(dst)); in emit_single_op()
80 return push_inst(compiler, INS_CLEAR_LEFT(dst, src2, 16)); in emit_single_op()
83 SLJIT_ASSERT(dst == src2); in emit_single_op()
[all …]
H A DsljitNativeMIPS_32.c46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
48 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
54 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
62 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
68 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \
72 sljit_s32 dst, sljit_s32 src1, sljit_sw src2) in emit_single_op() argument
82 if (dst != src2) in emit_single_op()
[all …]
H A DsljitNativePPC_64.c128 FAIL_IF(push_inst(compiler, EXTSW | S(src2) | A(TMP_REG2))); \
129 src2 = TMP_REG2; \
139 FAIL_IF(push_inst(compiler, EXTSW | S(src2) | A(TMP_REG2))); \
140 src2 = TMP_REG2; \
151 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) in emit_single_op() argument
157 if (dst != src2) in emit_single_op()
158 return push_inst(compiler, OR | S(src2) | A(dst) | B(src2)); in emit_single_op()
166 return push_inst(compiler, EXTSW | S(src2) | A(dst)); in emit_single_op()
167 return push_inst(compiler, INS_CLEAR_LEFT(dst, src2, 0)); in emit_single_op()
170 SLJIT_ASSERT(dst == src2); in emit_single_op()
[all …]
H A DsljitNativeMIPS_64.c129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
131 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
137 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
142 if (src2 >= 32) { \
145 src2 -= 32; \
150 FAIL_IF(push_inst(compiler, ins | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
152 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
159 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \
[all …]
H A DsljitNativeSPARC_32.c38 #define ARG2(flags, src2) ((flags & SRC2_IMM) ? IMM(src2) : S2(src2)) argument
41 sljit_s32 dst, sljit_s32 src1, sljit_sw src2) in emit_single_op() argument
51 if (dst != src2) in emit_single_op()
52 return push_inst(compiler, OR | D(dst) | S1(0) | S2(src2), DR(dst)); in emit_single_op()
60 return push_inst(compiler, AND | D(dst) | S1(src2) | IMM(0xff), DR(dst)); in emit_single_op()
61 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); in emit_single_op()
64 else if (dst != src2) in emit_single_op()
72 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); in emit_single_op()
75 else if (dst != src2) in emit_single_op()
81 …return push_inst(compiler, XNOR | (flags & SET_FLAGS) | D(dst) | S1(0) | S2(src2), DR(dst) | (flag… in emit_single_op()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Damxint8intrin.h38 #define _tile_int8_dp_internal(name,dst,src1,src2) \ argument
40 …("{"#name"\t%%tmm"#src2", %%tmm"#src1", %%tmm"#dst"|"#name"\t%%tmm"#dst", %%tmm"#src1", %%tmm"#src…
42 #define _tile_dpbssd(dst,src1,src2) \ argument
43 _tile_int8_dp_internal (tdpbssd, dst, src1, src2)
45 #define _tile_dpbsud(dst,src1,src2) \ argument
46 _tile_int8_dp_internal (tdpbsud, dst, src1, src2)
48 #define _tile_dpbusd(dst,src1,src2) \ argument
49 _tile_int8_dp_internal (tdpbusd, dst, src1, src2)
51 #define _tile_dpbuud(dst,src1,src2) \ argument
52 _tile_int8_dp_internal (tdpbuud, dst, src1, src2)
/netbsd-src/external/gpl3/gcc.old/dist/libhsail-rt/rt/
H A Dbitstring.c40 __hsail_bitextract_u32 (uint32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u32() argument
42 BITEXTRACT (uint32_t, src0, src1, src2); in __hsail_bitextract_u32()
46 __hsail_bitextract_s32 (int32_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s32() argument
48 BITEXTRACT (int32_t, src0, src1, src2); in __hsail_bitextract_s32()
52 __hsail_bitextract_u64 (uint64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_u64() argument
54 BITEXTRACT (uint64_t, src0, src1, src2); in __hsail_bitextract_u64()
58 __hsail_bitextract_s64 (int64_t src0, uint32_t src1, uint32_t src2) in __hsail_bitextract_s64() argument
60 BITEXTRACT (int64_t, src0, src1, src2); in __hsail_bitextract_s64()
70 __hsail_bitinsert_u32 (uint32_t src0, uint32_t src1, uint32_t src2, in __hsail_bitinsert_u32() argument
73 BITINSERT (uint32_t, src0, src1, src2, src3); in __hsail_bitinsert_u32()
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dtic6x-opcode-table.h135 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
140 ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
145 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
151 ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
157 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
164 ENC(src2, reg, 1), ENC(dst, reg, 2)))
169 ENC(src2, reg, 1), ENC(dst, reg, 2)))
174 ENC(src2, reg, 1), ENC(dst, reg, 2)))
179 ENC(src2, reg, 1), ENC(dst, reg, 2)))
183 ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
[all …]
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dtic6x-opcode-table.h135 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
140 ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
145 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
151 ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
157 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
164 ENC(src2, reg, 1), ENC(dst, reg, 2)))
169 ENC(src2, reg, 1), ENC(dst, reg, 2)))
174 ENC(src2, reg, 1), ENC(dst, reg, 2)))
179 ENC(src2, reg, 1), ENC(dst, reg, 2)))
183 ENC4(ENC(s, fu, 0), ENC(src1, scst, 0), ENC(src2, reg, 1),
[all …]

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