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Searched refs:reg0 (Results 1 – 25 of 80) sorted by relevance

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/netbsd-src/external/gpl3/gcc.old/dist/gcc/
H A Dauto-inc-dec.c318 rtx reg0; member
343 REGNO (inc_insn.reg0), (int) inc_insn.reg1_val); in dump_inc_insn()
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1)); in dump_inc_insn()
378 rtx reg0; member
396 REGNO (mem_insn.reg0), (int) mem_insn.reg1_val); in dump_mem_insn()
400 REGNO (mem_insn.reg0), REGNO (mem_insn.reg1)); in dump_mem_insn()
495 emit_move_insn (inc_insn.reg_res, inc_insn.reg0); in attempt_change()
533 regno = REGNO (inc_insn.reg0); in attempt_change()
538 move_dead_notes (mov_insn, mem_insn.insn, inc_insn.reg0); in attempt_change()
540 move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); in attempt_change()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A Dauto-inc-dec.cc318 rtx reg0; member
343 REGNO (inc_insn.reg0), (int) inc_insn.reg1_val); in dump_inc_insn()
348 REGNO (inc_insn.reg0), REGNO (inc_insn.reg1)); in dump_inc_insn()
378 rtx reg0; member
396 REGNO (mem_insn.reg0), (int) mem_insn.reg1_val); in dump_mem_insn()
400 REGNO (mem_insn.reg0), REGNO (mem_insn.reg1)); in dump_mem_insn()
495 emit_move_insn (inc_insn.reg_res, inc_insn.reg0); in attempt_change()
533 regno = REGNO (inc_insn.reg0); in attempt_change()
538 move_dead_notes (mov_insn, mem_insn.insn, inc_insn.reg0); in attempt_change()
540 move_dead_notes (mov_insn, inc_insn.insn, inc_insn.reg0); in attempt_change()
[all …]
/netbsd-src/crypto/external/bsd/openssl/dist/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
489 reg0 = GET_U32_BE(in, 0); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
511 reg0 = rk->u[0] ^ MAKE_U32( in ossl_aria_encrypt()
[all …]
/netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in aria_encrypt() local
489 reg0 = GET_U32_BE(in, 0); in aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in aria_encrypt()
511 reg0 = rk->u[0] ^ MAKE_U32( in aria_encrypt()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A Dselect-saddo.mir17 ; CHECK: %reg0:gpr32 = COPY $w0
19 ; CHECK: %saddo:gpr32 = ADDSWrr %reg0, %reg1, implicit-def $nzcv
23 %reg0:gpr(s32) = COPY $w0
25 %saddo:gpr(s32), %4:gpr(s1) = G_SADDO %reg0, %reg1
42 ; CHECK: %reg0:gpr64 = COPY $x0
44 ; CHECK: %saddo:gpr64 = ADDSXrr %reg0, %reg1, implicit-def $nzcv
48 %reg0:gpr(s64) = COPY $x0
50 %saddo:gpr(s64), %4:gpr(s1) = G_SADDO %reg0, %reg1
93 ; CHECK: %reg0:gpr32 = COPY $w0
95 ; CHECK: %add:gpr32 = ADDSWrs %reg0, %reg1, 16, implicit-def $nzcv
[all …]
H A Dselect-ssubo.mir17 ; CHECK: %reg0:gpr32 = COPY $w0
19 ; CHECK: %ssubo:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv
23 %reg0:gpr(s32) = COPY $w0
25 %ssubo:gpr(s32), %4:gpr(s1) = G_SSUBO %reg0, %reg1
42 ; CHECK: %reg0:gpr64 = COPY $x0
44 ; CHECK: %ssubo:gpr64 = SUBSXrr %reg0, %reg1, implicit-def $nzcv
48 %reg0:gpr(s64) = COPY $x0
50 %ssubo:gpr(s64), %4:gpr(s1) = G_SSUBO %reg0, %reg1
93 ; CHECK: %reg0:gpr32 = COPY $w0
95 ; CHECK: %sub:gpr32 = SUBSWrs %reg0, %reg1, 16, implicit-def $nzcv
[all …]
/netbsd-src/sys/dev/ic/
H A Drtwvar.h123 rtw_barrier(const struct rtw_regs *r, int reg0, int reg1, int flags) in rtw_barrier() argument
125 bus_space_barrier(r->r_bt, r->r_bh, MIN(reg0, reg1), in rtw_barrier()
126 MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags); in rtw_barrier()
133 #define RTW_SYNC(regs, reg0, reg1) \ argument
134 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
137 #define RTW_WBW(regs, reg0, reg1) \ argument
138 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE)
141 #define RTW_WBR(regs, reg0, reg1) \ argument
142 rtw_barrier(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE)
145 #define RTW_RBR(regs, reg0, reg1) \ argument
[all …]
H A Dsmc83c170.c898 uint32_t genctl, reg0; in epic_init() local
931 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); in epic_init()
932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); in epic_init()
938 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); in epic_init()
943 reg0 = enaddr[1] << 8 | enaddr[0]; in epic_init()
944 bus_space_write_4(st, sh, EPIC_LAN0, reg0); in epic_init()
945 reg0 = enaddr[3] << 8 | enaddr[2]; in epic_init()
946 bus_space_write_4(st, sh, EPIC_LAN1, reg0); in epic_init()
947 reg0 = enaddr[5] << 8 | enaddr[4]; in epic_init()
948 bus_space_write_4(st, sh, EPIC_LAN2, reg0); in epic_init()
[all...]
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dload.s9 .macro load32 num:req, reg0:req, reg1:req
10 imm32 \reg0 \num
12 CC = \reg0 == \reg1
29 .macro load16z num:req reg0:req reg1:req
30 \reg0 = \num (Z);
32 CC = \reg0 == \reg1
48 .macro load16x num:req reg0:req reg1:req
49 \reg0 = \num (X);
51 CC = \reg0 == \reg1
H A Dmove.s9 .macro move reg0:req, reg1:req, clobber:req
10 imm32 \reg0, 0x5555aaaa
13 \reg0 = \reg1;
14 CC = \reg0 == \clobber;
/netbsd-src/sys/arch/hpcsh/dev/
H A Dpsh3lcd.c71 uint8_t reg0; member
142 for (i = 0; psh3lcd_x0_bcd[i].reg0 != 0; i++) in psh3lcd_x0_bcd_get()
143 if (bcr0 == psh3lcd_x0_bcd[i].reg0 && in psh3lcd_x0_bcd_get()
147 if (psh3lcd_x0_bcd[i].reg0 == 0) in psh3lcd_x0_bcd_get()
182 _reg_write_1(PSH3LCD_BRIGHTNESS_REG0, psh3lcd_x0_bcd[index].reg0); in psh3lcd_x0_set_brightness()
/netbsd-src/sys/arch/shark/shark/
H A Dns87307.c343 u_char reg0; in nsioConfigPrint() local
354 NSIO_READ_REG( nsioIot, nsioIoh, NSIO_CFG_REG0, reg0 ); in nsioConfigPrint()
364 printf("reg0: %x\n",reg0); in nsioConfigPrint()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_gmbus.c684 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); in do_gmbus_xfer()
690 gmbus0_source | bus->reg0); in do_gmbus_xfer()
694 gmbus0_source | bus->reg0, 0); in do_gmbus_xfer()
776 bus->adapter.name, bus->reg0 & 0xff); in do_gmbus_xfer()
961 bus->reg0 = pin | GMBUS_RATE_100KHZ; in intel_gmbus_setup()
1002 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; in intel_gmbus_set_speed()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_virt.c54 uint32_t reg0, uint32_t reg1, in amdgpu_virt_kiq_reg_write_reg_wait() argument
65 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, in amdgpu_virt_kiq_reg_write_reg_wait()
90 pr_err("failed to write reg %x wait reg %x\n", reg0, reg1); in amdgpu_virt_kiq_reg_write_reg_wait()
H A Damdgpu_ring.c401 uint32_t reg0, uint32_t reg1, in amdgpu_ring_emit_reg_write_reg_wait_helper() argument
404 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
H A Damdgpu_ring.h171 uint32_t reg0, uint32_t reg1,
274 uint32_t reg0, uint32_t val0,
/netbsd-src/sys/arch/mips/cavium/dev/
H A Docteon_pkovar.h91 octpko_cmd_word0(int sz1, int sz0, int s1, int reg1, int s0, int reg0, in octpko_cmd_word0() argument
101 __SHIFTIN(reg0, PKO_CMD_WORD0_REG0) | in octpko_cmd_word0()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/cr16/
H A Dcr16.md365 int reg0 = REGNO (operands[0]);
367 xoperand = gen_rtx_REG (SImode, reg0 + 2);
660 int reg0 = REGNO (operands[0]);
663 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
665 if ((reg1 + 2) != reg0)
693 int reg0 = REGNO (operands[0]), reg1 = -2;
727 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
729 gcc_assert ((reg0 + 1) != reg1);
730 if (reg0 != reg1 && (reg1 + 1) != reg0)
/netbsd-src/external/gpl3/gcc/dist/gcc/config/cr16/
H A Dcr16.md365 int reg0 = REGNO (operands[0]);
367 xoperand = gen_rtx_REG (SImode, reg0 + 2);
660 int reg0 = REGNO (operands[0]);
663 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
665 if ((reg1 + 2) != reg0)
693 int reg0 = REGNO (operands[0]), reg1 = -2;
727 xoperands[0] = gen_rtx_REG (SImode, reg0 + 2);
729 gcc_assert ((reg0 + 1) != reg1);
730 if (reg0 != reg1 && (reg1 + 1) != reg0)
/netbsd-src/sys/dev/isa/
H A Dwbsio.c370 uint8_t reg0, reg1, rev; in wbsio_search() local
384 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_HM_ADDR_LSB); in wbsio_search()
390 iobase = (reg1 << 8) | (reg0 & ~0x7); in wbsio_search()
537 uint8_t reg0, reg1; in wbsio_gpio_rt_init() local
544 reg0 = wbsio_conf_read(sc->sc_iot, sc->sc_ioh, WBSIO_GPIO_ADDR_LSB); in wbsio_gpio_rt_init()
546 iobase = (reg1 << 8) | (reg0 & ~0x7); in wbsio_gpio_rt_init()
/netbsd-src/sys/arch/arm/rockchip/
H A Drk3588_iomux.c80 bus_size_t reg0; member
909 bus_size_t reg0 = rk3588_iomux_regmap[pin].reg0; in rk3588_iomux_set_mux() local
913 if (reg0 != 0) { in rk3588_iomux_set_mux()
915 syscon_write_4(sc->sc_grf, reg0, val); in rk3588_iomux_set_mux()
/netbsd-src/sys/arch/hpcmips/vr/
H A Dvrc4172gpio.c161 u_int16_t reg0, reg1; in read_4() local
163 reg0 = read_2(sc, off); in read_4()
166 return (reg0|(reg1<<16)); in read_4()
/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Dr128_drv.h407 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ argument
408 (((reg1) >> 2) << 11) | ((reg0) >> 2))
/netbsd-src/sys/external/bsd/drm2/dist/drm/r128/
H A Dr128_drv.h423 #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \ argument
424 (((reg1) >> 2) << 11) | ((reg0) >> 2))
/netbsd-src/sys/external/bsd/drm2/dist/drm/mga/
H A Dmga_drv.h342 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ argument
344 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \

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