| /netbsd-src/sys/arch/arm/amlogic/ |
| H A D | meson_clk_mpll.c | 45 struct meson_clk_mpll *mpll = &clk->u.mpll; in meson_clk_mpll_get_rate() local
63 val = CLK_READ(sc, mpll->sdm.reg); in meson_clk_mpll_get_rate()
64 sdm = __SHIFTOUT(val, mpll->sdm.mask); in meson_clk_mpll_get_rate()
66 val = CLK_READ(sc, mpll->n2.reg); in meson_clk_mpll_get_rate()
67 n2 = __SHIFTOUT(val, mpll->n2.mask); in meson_clk_mpll_get_rate()
82 struct meson_clk_mpll *mpll = &clk->u.mpll; in meson_clk_mpll_get_parent() local
86 return mpll->parent; in meson_clk_mpll_get_parent()
|
| H A D | meson_clk.h | 320 .u.mpll.parent = (_parent), \
321 .u.mpll.sdm = _sdm, \
322 .u.mpll.sdm_enable = _sdm_enable, \
323 .u.mpll.n2 = _n2, \
324 .u.mpll.ssen = _ssen, \
325 .u.mpll.flags = (_flags), \
342 struct meson_clk_mpll mpll; member
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_clocks.c | 77 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
83 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
117 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
155 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
156 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
192 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
224 if (mpll->reference_div < 2) in radeon_get_clock_info()
225 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
239 mpll->reference_freq = 1432; in radeon_get_clock_info()
244 mpll->reference_freq = 2700; in radeon_get_clock_info()
[all …]
|
| H A D | radeon_combios.c | 745 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_combios_get_clock_info() local
786 mpll->reference_freq = RBIOS16(pll_info + 0x26); in radeon_combios_get_clock_info()
787 mpll->reference_div = RBIOS16(pll_info + 0x28); in radeon_combios_get_clock_info()
788 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); in radeon_combios_get_clock_info()
789 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); in radeon_combios_get_clock_info()
792 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); in radeon_combios_get_clock_info()
793 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); in radeon_combios_get_clock_info()
796 mpll->pll_in_min = 40; in radeon_combios_get_clock_info()
797 mpll->pll_in_max = 500; in radeon_combios_get_clock_info()
|
| H A D | radeon_atombios.c | 1144 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_atom_get_clock_info() local
1223 mpll->reference_freq = in radeon_atom_get_clock_info()
1226 mpll->reference_freq = in radeon_atom_get_clock_info()
1228 mpll->reference_div = 0; in radeon_atom_get_clock_info()
1230 mpll->pll_out_min = in radeon_atom_get_clock_info()
1232 mpll->pll_out_max = in radeon_atom_get_clock_info()
1236 if (mpll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1238 mpll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1240 mpll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1243 mpll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
|
| H A D | radeon_rv740_dpm.c | 256 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv740_populate_mclk_value()
|
| H A D | radeon_rv730_dpm.c | 176 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv730_populate_mclk_value()
|
| H A D | radeon_cypress_dpm.c | 449 u32 ref_clk = rdev->clock.mpll.reference_freq; in cypress_map_clkf_to_ibias()
565 u32 reference_clock = rdev->clock.mpll.reference_freq; in cypress_populate_mclk_value()
|
| H A D | radeon_rv6xx_dpm.c | 660 u32 ref_clk = rdev->clock.mpll.reference_freq; in rv6xx_program_mclk_spread_spectrum_parameters()
|
| H A D | radeon_rv770_dpm.c | 408 u32 reference_clock = rdev->clock.mpll.reference_freq; in rv770_populate_mclk_value()
|
| H A D | radeon.h | 284 struct radeon_pll mpll; member
|
| H A D | radeon_ni_dpm.c | 2246 u32 reference_clock = rdev->clock.mpll.reference_freq; in ni_populate_mclk_value()
|
| H A D | radeon_si_dpm.c | 4921 u32 reference_clock = rdev->clock.mpll.reference_freq; in si_populate_mclk_value()
|
| H A D | radeon_ci_dpm.c | 2837 u32 reference_clock = rdev->clock.mpll.reference_freq; in ci_calculate_mclk_params()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_atomfirmware.c | 351 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atomfirmware_get_clock_info() local
411 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
413 mpll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
414 mpll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
415 mpll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
416 mpll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
417 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
418 mpll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
419 mpll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
420 mpll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
|
| H A D | amdgpu_atombios.c | 578 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info() local
650 mpll->reference_freq = in amdgpu_atombios_get_clock_info()
652 mpll->reference_div = 0; in amdgpu_atombios_get_clock_info()
654 mpll->pll_out_min = in amdgpu_atombios_get_clock_info()
656 mpll->pll_out_max = in amdgpu_atombios_get_clock_info()
660 if (mpll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
661 mpll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
663 mpll->pll_in_min = in amdgpu_atombios_get_clock_info()
665 mpll->pll_in_max = in amdgpu_atombios_get_clock_info()
673 mpll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
|
| H A D | amdgpu.h | 339 struct amdgpu_pll mpll; member
|
| H A D | amdgpu_si_dpm.c | 5385 u32 reference_clock = adev->clock.mpll.reference_freq; in si_populate_mclk_value()
|
| /netbsd-src/sys/arch/mips/ingenic/ |
| H A D | apbus.c | 129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv; in apbus_attach() local
142 mpll = readreg(JZ_CPMPCR); in apbus_attach()
143 m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S; in apbus_attach()
144 n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S; in apbus_attach()
145 p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S; in apbus_attach()
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| H A D | nouveau_nvkm_subdev_devinit_nv04.c | 293 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
296 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
311 if (mpll) { in setPLL_double_lowregs()
327 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
331 if (mpll) { in setPLL_double_lowregs()
345 if (mpll) { in setPLL_double_lowregs()
354 if (mpll) { in setPLL_double_lowregs()
|
| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | mstar-v7.dtsi | 9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
142 mpll: mpll@206000 { label
143 compatible = "mstar,msc313-mpll";
|
| H A D | exynos4412.dtsi | 659 "mcuispdiv1", "mpll", "aclk200",
|
| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| H A D | sharkl3.dtsi | 91 mpll: mpll { label
92 compatible = "sprd,sc9863a-mpll";
|
| /netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| H A D | nouveau_nvkm_subdev_fb_ramnv50.c | 231 struct nvbios_pll mpll; in nv50_ram_calc() local
333 ret = nvbios_pll_parse(bios, 0x004008, &mpll); in nv50_ram_calc()
334 mpll.vco2.max_freq = 0; in nv50_ram_calc()
336 ret = nv04_pll_calc(subdev, &mpll, freq, in nv50_ram_calc()
354 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); in nv50_ram_calc()
|